Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers ... Make synthesis parameters accessible for the drivers. Rework implementation to reflect the parameters of the actual core and not of the AXI interfacing core.		2021-02-05 15:24:15 +02:00
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Makefile	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
axi_jesd204_tx.v	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
axi_jesd204_tx_constr.sdc	jesd204: Fix constraints for axi_jesd_tx	2018-05-10 18:17:32 +03:00
axi_jesd204_tx_constr.xdc	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
axi_jesd204_tx_hw.tcl	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
axi_jesd204_tx_ip.tcl	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
axi_jesd204_tx_ooc.ttcl	jesd204:axi_jesd204_tx: set OOC default clock constraints	2019-04-22 10:27:16 +03:00
jesd204_up_tx.v	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00