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Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 		2022-06-28 18:06:56 +03:00
..
ccbob_cmos projects: Update .v files according to guideline 2022-06-28 18:06:56 +03:00
ccbob_lvds projects: Update .v files according to guideline 2022-06-28 18:06:56 +03:00
ccpackrf_lvds projects: Update .v files according to guideline 2022-06-28 18:06:56 +03:00
common adrv9364: Added sysid to all projects 2019-11-20 10:43:54 +02:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Readme.md start adding some doc to the ./projects directory 2021-11-10 14:01:06 +02:00

Readme.md

ADRV9364Z7020 SDR SOM

This folder contains the ADRV9364Z7020 SOM projects for each of the carrier boards.

Supported SOM & Carriers

Directory Description
ccbob_cmos ADRV9364Z7020-SOM (CMOS Mode) + ADRV1CRR-BOB
ccbob_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-BOB
ccpackrf_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-PACKRF
ccusb_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-USB

Board Design Files (Vivado IPI)

Directory/File Description
common/ADRV9364Z7020_bd.tcl ADRV9364Z7020-SOM board design file.
common/ccbob_bd.tcl carrier, break out board design file.
common/ccpackrf_bd.tcl carrier, packrf board design file.
common/ccusb_bd.tcl carrier, usb board design file.

FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.

Board Constraint Files (pin-out & io-standard)

Directory/File Description
common/ADRV9364Z7020_constr.xdc ADRV9364Z7020-SOM base constraints file.
common/ADRV9364Z7020_constr_cmos.xdc ADRV9364Z7020-SOM CMOS mode constraints file.
common/ADRV9364Z7020_constr_lvds.xdc ADRV9364Z7020-SOM LVDS mode constraints file.
common/ccbob_constr.xdc carrier, break out board constraints file.
common/ccpackrf_constr.xdc carrier, packrf board constraints file.
common/ccusb_constr.xdc carrier, usb board constraints file.

FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.

Building, Generating Bit Files (easy & efficient method)

[some-directory]> git clone -b dev git@github.com:analogdevicesinc/hdl.git
[some-directory]> make -C hdl/projects/adrv9364z7020/ccbob_cmos

Building, Generating Elf Files (easy & efficient method)

[some-directory]> git clone -b dev git@github.com:analogdevicesinc/no-OS.git
[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos

Running, a quick test (easy & efficient method)

[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos run

ADRV9364Z7020 HDL Project

Here are some pointers to help you: