Istvan Csomortani 1d4b92190a fmcomms2/zc702: Fix Warning[Synth 8-2611] ... In Verilog-2001 standard, redeclaration of an output port as a wire is not allowed.		2017-04-19 13:54:03 +03:00
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Makefile	make updates	2017-03-20 16:05:18 -04:00
system_bd.tcl	ad9361- delay initialization	2017-03-15 12:06:59 -04:00
system_constr.xdc	fmcomms2/zc702: Fix critical warnings	2016-12-08 19:54:52 +02:00
system_project.tcl	move/rename - delay script belongs to ad9361	2017-03-10 12:44:32 -05:00
system_top.v	fmcomms2/zc702: Fix Warning[Synth 8-2611]	2017-04-19 13:54:03 +03:00