48 lines
2.0 KiB
Tcl
48 lines
2.0 KiB
Tcl
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# unused
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ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
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ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
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# GPS-UART
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set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen]
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT false] $sys_audio_clkgen
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set_property -dict [list CONFIG.PRIM_SOURCE No_buffer] $sys_audio_clkgen
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set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
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set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
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set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
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ad_connect sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX
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ad_connect sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX
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ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
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ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
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ad_connect i2s axi_i2s_adi/I2S
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ad_cpu_interconnect 0x77600000 axi_i2s_adi
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