960c711f3b
The axi_dmac core is now capable of detecting whether its different parts run in different clock domains or not. No need to configure it manually any more. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.