226 lines
7.8 KiB
Verilog
Executable File
226 lines
7.8 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9122_dds (
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// dac interface
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dac_div_clk,
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dac_rst,
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dac_dds_data_0,
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dac_dds_data_1,
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dac_dds_data_2,
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dac_dds_data_3,
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// processor interface
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dac_dds_enable,
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dac_dds_format,
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dac_dds_pattenb,
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dac_dds_patt_1,
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dac_dds_init_1,
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dac_dds_incr_1,
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dac_dds_scale_1,
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dac_dds_patt_2,
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dac_dds_init_2,
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dac_dds_incr_2,
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dac_dds_scale_2);
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// parameters
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parameter DP_DISABLE = 0;
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// dac interface
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input dac_div_clk;
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input dac_rst;
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output [15:0] dac_dds_data_0;
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output [15:0] dac_dds_data_1;
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output [15:0] dac_dds_data_2;
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output [15:0] dac_dds_data_3;
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// processor interface
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input dac_dds_enable;
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input dac_dds_format;
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input dac_dds_pattenb;
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input [15:0] dac_dds_patt_1;
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input [15:0] dac_dds_init_1;
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input [15:0] dac_dds_incr_1;
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input [15:0] dac_dds_scale_1;
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input [15:0] dac_dds_patt_2;
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input [15:0] dac_dds_init_2;
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input [15:0] dac_dds_incr_2;
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input [15:0] dac_dds_scale_2;
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// internal registers
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reg [15:0] dac_dds_phase_0_0 = 'd0;
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reg [15:0] dac_dds_phase_0_1 = 'd0;
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reg [15:0] dac_dds_phase_1_0 = 'd0;
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reg [15:0] dac_dds_phase_1_1 = 'd0;
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reg [15:0] dac_dds_phase_2_0 = 'd0;
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reg [15:0] dac_dds_phase_2_1 = 'd0;
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reg [15:0] dac_dds_phase_3_0 = 'd0;
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reg [15:0] dac_dds_phase_3_1 = 'd0;
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reg [15:0] dac_dds_data_0 = 'd0;
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reg [15:0] dac_dds_data_1 = 'd0;
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reg [15:0] dac_dds_data_2 = 'd0;
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reg [15:0] dac_dds_data_3 = 'd0;
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// internal signals
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wire [15:0] dac_dds_data_0_s;
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wire [15:0] dac_dds_data_1_s;
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wire [15:0] dac_dds_data_2_s;
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wire [15:0] dac_dds_data_3_s;
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// dds phase counters
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always @(posedge dac_div_clk) begin
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if (dac_dds_enable == 1'b0) begin
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dac_dds_phase_0_0 <= dac_dds_init_1;
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dac_dds_phase_0_1 <= dac_dds_init_2;
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dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1;
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dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2;
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dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1;
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dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2;
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dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1;
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dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2;
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end else begin
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dac_dds_phase_0_0 <= dac_dds_phase_0_0 + {dac_dds_incr_1[13:0], 2'd0};
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dac_dds_phase_0_1 <= dac_dds_phase_0_1 + {dac_dds_incr_2[13:0], 2'd0};
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dac_dds_phase_1_0 <= dac_dds_phase_1_0 + {dac_dds_incr_1[13:0], 2'd0};
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dac_dds_phase_1_1 <= dac_dds_phase_1_1 + {dac_dds_incr_2[13:0], 2'd0};
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dac_dds_phase_2_0 <= dac_dds_phase_2_0 + {dac_dds_incr_1[13:0], 2'd0};
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dac_dds_phase_2_1 <= dac_dds_phase_2_1 + {dac_dds_incr_2[13:0], 2'd0};
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dac_dds_phase_3_0 <= dac_dds_phase_3_0 + {dac_dds_incr_1[13:0], 2'd0};
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dac_dds_phase_3_1 <= dac_dds_phase_3_1 + {dac_dds_incr_2[13:0], 2'd0};
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end
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end
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// output is either 2's complement or offset binary.
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always @(posedge dac_div_clk) begin
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if (dac_dds_pattenb == 1'b1) begin
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dac_dds_data_0 <= dac_dds_patt_1;
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dac_dds_data_1 <= dac_dds_patt_2;
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dac_dds_data_2 <= dac_dds_patt_1;
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dac_dds_data_3 <= dac_dds_patt_2;
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end else begin
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dac_dds_data_0 <= dac_dds_data_0_s;
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dac_dds_data_1 <= dac_dds_data_1_s;
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dac_dds_data_2 <= dac_dds_data_2_s;
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dac_dds_data_3 <= dac_dds_data_3_s;
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end
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end
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// dds
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generate
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if (DP_DISABLE == 1) begin
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assign dac_dds_data_0_s = 16'd0;
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end else begin
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ad_dds i_dds_0 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_enable (dac_dds_enable),
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.dds_phase_0 (dac_dds_phase_0_0),
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.dds_scale_0 (dac_dds_scale_1),
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.dds_phase_1 (dac_dds_phase_0_1),
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.dds_scale_1 (dac_dds_scale_2),
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.dds_data (dac_dds_data_0_s));
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end
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endgenerate
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generate
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if (DP_DISABLE == 1) begin
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assign dac_dds_data_1_s = 16'd0;
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end else begin
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ad_dds i_dds_1 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_enable (dac_dds_enable),
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.dds_phase_0 (dac_dds_phase_1_0),
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.dds_scale_0 (dac_dds_scale_1),
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.dds_phase_1 (dac_dds_phase_1_1),
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.dds_scale_1 (dac_dds_scale_2),
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.dds_data (dac_dds_data_1_s));
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end
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endgenerate
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generate
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if (DP_DISABLE == 1) begin
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assign dac_dds_data_2_s = 16'd0;
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end else begin
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ad_dds i_dds_2 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_enable (dac_dds_enable),
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.dds_phase_0 (dac_dds_phase_2_0),
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.dds_scale_0 (dac_dds_scale_1),
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.dds_phase_1 (dac_dds_phase_2_1),
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.dds_scale_1 (dac_dds_scale_2),
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.dds_data (dac_dds_data_2_s));
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end
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endgenerate
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generate
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if (DP_DISABLE == 1) begin
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assign dac_dds_data_3_s = 16'd0;
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end else begin
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ad_dds i_dds_3 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_enable (dac_dds_enable),
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.dds_phase_0 (dac_dds_phase_3_0),
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.dds_scale_0 (dac_dds_scale_1),
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.dds_phase_1 (dac_dds_phase_3_1),
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.dds_scale_1 (dac_dds_scale_2),
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.dds_data (dac_dds_data_3_s));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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