373 lines
10 KiB
Verilog
373 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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sgmii_rxp,
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sgmii_rxn,
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sgmii_txp,
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sgmii_txn,
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phy_rstn,
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mgt_clk_p,
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mgt_clk_n,
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mdio_mdc,
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mdio_mdio,
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fan_pwm,
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linear_flash_addr,
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linear_flash_adv_ldn,
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linear_flash_ce_n,
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linear_flash_oen,
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linear_flash_wen,
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linear_flash_dq_io,
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gpio_lcd,
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gpio_bd,
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iic_rstn,
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iic_scl,
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iic_sda,
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dac_clk_in_p,
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dac_clk_in_n,
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dac_clk_out_p,
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dac_clk_out_n,
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dac_frame_out_p,
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dac_frame_out_n,
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dac_data_out_p,
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dac_data_out_n,
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adc_clk_in_p,
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adc_clk_in_n,
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adc_or_in_p,
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adc_or_in_n,
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adc_data_in_p,
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adc_data_in_n,
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ref_clk_out_p,
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ref_clk_out_n );
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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input sgmii_rxp;
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input sgmii_rxn;
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output sgmii_txp;
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output sgmii_txn;
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output phy_rstn;
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input mgt_clk_p;
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input mgt_clk_n;
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output mdio_mdc;
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inout mdio_mdio;
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output fan_pwm;
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output [26:1] linear_flash_addr;
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output linear_flash_adv_ldn;
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output linear_flash_ce_n;
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output linear_flash_oen;
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output linear_flash_wen;
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inout [15:0] linear_flash_dq_io;
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inout [ 6:0] gpio_lcd;
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inout [20:0] gpio_bd;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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input dac_clk_in_p;
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input dac_clk_in_n;
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output dac_clk_out_p;
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output dac_clk_out_n;
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output dac_frame_out_p;
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output dac_frame_out_n;
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output [15:0] dac_data_out_p;
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output [15:0] dac_data_out_n;
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input adc_clk_in_p;
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input adc_clk_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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output ref_clk_out_p;
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output ref_clk_out_n;
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// internal registers
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reg [63:0] dac_ddata_0 = 'd0;
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reg [63:0] dac_ddata_1 = 'd0;
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reg dac_dma_rd = 'd0;
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reg adc_data_cnt = 'd0;
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reg adc_dma_wr = 'd0;
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reg [31:0] adc_dma_wdata = 'd0;
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 7:0] spi_csn;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire dac_clk;
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wire dac_valid_0;
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wire dac_enable_0;
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wire dac_valid_1;
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wire dac_enable_1;
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wire [63:0] dac_dma_rdata;
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wire adc_clk;
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wire adc_valid_0;
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wire adc_enable_0;
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wire [15:0] adc_data_0;
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wire adc_valid_1;
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wire adc_enable_1;
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wire [15:0] adc_data_1;
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wire ref_clk;
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wire oddr_ref_clk;
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// assignments
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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// instantiations
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_oddr_ref_clk (
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.S (1'b0),
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.CE (1'b1),
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.R (1'b0),
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.C (ref_clk),
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.D1 (1'b1),
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.D2 (1'b0),
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.Q (oddr_ref_clk));
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OBUFDS i_obufds_ref_clk (
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.I (oddr_ref_clk),
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.O (ref_clk_out_p),
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.OB (ref_clk_out_n));
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always @(posedge dac_clk) begin
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dac_dma_rd <= dac_valid_0 & dac_enable_0;
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dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
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dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
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dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
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dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
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dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
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dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
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dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
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dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
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end
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always @(posedge adc_clk) begin
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adc_data_cnt <= ~adc_data_cnt;
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case ({adc_enable_1, adc_enable_0})
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2'b10: begin
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adc_dma_wr <= adc_data_cnt;
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adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
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end
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2'b01: begin
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adc_dma_wr <= adc_data_cnt;
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adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
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end
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default: begin
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adc_dma_wr <= 1'b1;
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adc_dma_wdata <= {adc_data_1, adc_data_0};
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end
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endcase
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end
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ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
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.dt (gpio_t[20:0]),
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.di (gpio_o[20:0]),
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.do (gpio_i[20:0]),
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.dio(gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.linear_flash_dq_io(linear_flash_dq_io),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio_lcd_tri_io (gpio_lcd),
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.adc_clk (adc_clk),
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.adc_clk_in_n (adc_clk_in_n),
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.adc_clk_in_p (adc_clk_in_p),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_in_n (adc_data_in_n),
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.adc_data_in_p (adc_data_in_p),
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.adc_dma_wdata (adc_dma_wdata),
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.adc_dma_wr (adc_dma_wr),
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.adc_enable_0 (adc_enable_0),
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.adc_enable_1 (adc_enable_1),
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.adc_or_in_n (adc_or_in_n),
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.adc_or_in_p (adc_or_in_p),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.dac_clk (dac_clk),
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.dac_clk_in_n (dac_clk_in_n),
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.dac_clk_in_p (dac_clk_in_p),
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.dac_clk_out_n (dac_clk_out_n),
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.dac_clk_out_p (dac_clk_out_p),
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.dac_data_out_n (dac_data_out_n),
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.dac_data_out_p (dac_data_out_p),
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.dac_ddata_0 (dac_ddata_0),
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.dac_ddata_1 (dac_ddata_1),
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.dac_dma_rd (dac_dma_rd),
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.dac_dma_rdata (dac_dma_rdata),
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.dac_enable_0 (dac_enable_0),
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.dac_enable_1 (dac_enable_1),
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.dac_frame_out_n (dac_frame_out_n),
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.dac_frame_out_p (dac_frame_out_p),
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.dac_valid_0 (dac_valid_0),
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.dac_valid_1 (dac_valid_1),
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.ref_clk (ref_clk),
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.mb_intr_06 (1'b0),
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.mb_intr_07 (1'b0),
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.mb_intr_08 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mgt_clk_clk_n (mgt_clk_n),
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.mgt_clk_clk_p (mgt_clk_p),
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.phy_rstn (phy_rstn),
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.phy_sd (1'b1),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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.sgmii_txp (sgmii_txp),
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.spi_clk_i (1'b0),
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.spi_clk_o (spi_clk),
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.spi_csn_i (8'hff),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (1'b0),
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.spi_sdo_o (spi_mosi),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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