511 lines
14 KiB
Verilog
511 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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iic_scl,
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iic_sda,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_p,
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rx_sync_n,
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rx_data_p,
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rx_data_n,
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spi_fout_enb_clk,
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spi_fout_enb_mlo,
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spi_fout_enb_rst,
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spi_fout_enb_sync,
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spi_fout_enb_sysref,
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spi_fout_enb_trig,
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spi_fout_clk,
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spi_fout_sdio,
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spi_afe_csn,
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spi_afe_clk,
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spi_afe_sdio,
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spi_clk_csn,
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spi_clk_clk,
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spi_clk_sdio,
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afe_rst_p,
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afe_rst_n,
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afe_trig_p,
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afe_trig_n,
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dac_sleep,
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dac_data,
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afe_pdn,
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afe_stby,
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clk_resetn,
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clk_syncn,
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clk_status,
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amp_disbn,
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prc_sck,
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prc_cnv,
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prc_sdo_i,
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prc_sdo_q);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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inout iic_scl;
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inout iic_sda;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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output rx_sysref_p;
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output rx_sysref_n;
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output rx_sync_p;
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output rx_sync_n;
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input [ 7:0] rx_data_p;
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input [ 7:0] rx_data_n;
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output spi_fout_enb_clk;
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output spi_fout_enb_mlo;
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output spi_fout_enb_rst;
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output spi_fout_enb_sync;
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output spi_fout_enb_sysref;
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output spi_fout_enb_trig;
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output spi_fout_clk;
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output spi_fout_sdio;
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output [ 3:0] spi_afe_csn;
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output spi_afe_clk;
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inout spi_afe_sdio;
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output spi_clk_csn;
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output spi_clk_clk;
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inout spi_clk_sdio;
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output afe_rst_p;
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output afe_rst_n;
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output afe_trig_p;
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output afe_trig_n;
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output dac_sleep;
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output [13:0] dac_data;
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output afe_pdn;
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output afe_stby;
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output clk_resetn;
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output clk_syncn;
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input clk_status;
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output amp_disbn;
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inout prc_sck;
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inout prc_cnv;
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inout prc_sdo_i;
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inout prc_sdo_q;
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// internal signals
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wire [ 4:0] spi_csn;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire [511:0] adc_data;
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wire [127:0] adc_data_0;
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wire [127:0] adc_data_1;
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wire [127:0] adc_data_2;
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wire [127:0] adc_data_3;
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wire adc_valid;
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wire [ 7:0] adc_valid_0;
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wire [ 7:0] adc_valid_1;
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wire [ 7:0] adc_valid_2;
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wire [ 7:0] adc_valid_3;
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wire [ 7:0] adc_enable_0;
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wire [ 7:0] adc_enable_1;
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wire [ 7:0] adc_enable_2;
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wire [ 7:0] adc_enable_3;
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wire adc_dovf;
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wire adc_dovf_0;
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wire adc_dovf_1;
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wire adc_dovf_2;
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wire adc_dovf_3;
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wire [255:0] gt_rx_data;
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wire [7:0] gt_rx_sof;
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wire [63:0] gt_rx_data_0;
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wire gt_rx_sof_0;
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wire [63:0] gt_rx_data_1;
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wire gt_rx_sof_1;
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wire [63:0] gt_rx_data_2;
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wire gt_rx_sof_2;
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wire [63:0] gt_rx_data_3;
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wire gt_rx_sof_3;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [15:0] ps_intrs;
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// spi assignments
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assign spi_fout_enb_clk = 1'b0;
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assign spi_fout_enb_mlo = 1'b0;
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assign spi_fout_enb_rst = 1'b0;
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assign spi_fout_enb_sync = 1'b0;
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assign spi_fout_enb_sysref = 1'b0;
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assign spi_fout_enb_trig = 1'b0;
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assign spi_fout_sdio = 1'b0;
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assign spi_afe_csn = spi_csn[ 4: 1];
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assign spi_clk_csn = spi_csn[ 0: 0];
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assign spi_fout_clk = 1'b0;
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assign spi_afe_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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usdrx1_spi i_spi (
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.spi_afe_csn (spi_csn[4:1]),
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.spi_clk_csn (spi_csn[0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_afe_sdio (spi_afe_sdio),
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.spi_clk_sdio (spi_clk_sdio));
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// single dma for all channels
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assign gt_rx_data_3 = gt_rx_data[255:192];
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assign gt_rx_data_2 = gt_rx_data[191:128];
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assign gt_rx_data_1 = gt_rx_data[127: 64];
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assign gt_rx_data_0 = gt_rx_data[ 63: 0];
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assign gt_rx_sof_0 = gt_rx_sof [0] | gt_rx_sof [1];
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assign gt_rx_sof_1 = gt_rx_sof [2] | gt_rx_sof [3];
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assign gt_rx_sof_2 = gt_rx_sof [4] | gt_rx_sof [5];
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assign gt_rx_sof_3 = gt_rx_sof [6] | gt_rx_sof [7];
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assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
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assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ;
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assign adc_dovf_0 = adc_dovf;
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assign adc_dovf_1 = adc_dovf;
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assign adc_dovf_2 = adc_dovf;
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assign adc_dovf_3 = adc_dovf;
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// data interface
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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OBUFDS i_obufds_rx_sysref (
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.I (rx_sysref),
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.O (rx_sysref_p),
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.OB (rx_sysref_n));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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// gpio/control interface
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IOBUF i_iobuf_gpio_prc_sdo_q (
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.I (gpio_o[43]),
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.O (gpio_i[43]),
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.T (gpio_t[43]),
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.IO (prc_sdo_q));
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IOBUF i_iobuf_gpio_prc_sdo_i (
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.I (gpio_o[42]),
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.O (gpio_i[42]),
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.T (gpio_t[42]),
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.IO (prc_sdo_i));
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IOBUF i_iobuf_gpio_prc_cnv (
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.I (gpio_o[41]),
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.O (gpio_i[41]),
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.T (gpio_t[41]),
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.IO (prc_cnv));
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IOBUF i_iobuf_gpio_prc_sck (
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.I (gpio_o[40]),
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.O (gpio_i[40]),
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.T (gpio_t[40]),
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.IO (prc_sck));
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assign dac_sleep = gpio_o[44];
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assign amp_disbn = gpio_o[39];
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assign gpio_i[38] = clk_status;
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assign clk_syncn = gpio_o[37];
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assign clk_resetn = gpio_o[36];
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assign afe_stby = gpio_o[35];
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assign afe_pdn = gpio_o[34];
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OBUFDS i_obufds_gpio_afe_trig (
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.I (gpio_o[33]),
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.O (afe_trig_p),
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.OB (afe_trig_n));
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OBUFDS i_obufds_gpio_afe_rst (
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.I (gpio_o[32]),
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.O (afe_rst_p),
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.OB (afe_rst_n));
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genvar n;
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generate
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for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data
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assign dac_data[n] = gpio_o[45+n];
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end
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for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
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IOBUF i_iobuf_gpio_bd (
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.I (gpio_o[n]),
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.O (gpio_i[n]),
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.T (gpio_t[n]),
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.IO (gpio_bd[n]));
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end
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endgenerate
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system_wrapper i_system_wrapper (
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.adc_data (adc_data),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_2 (adc_data_2),
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.adc_data_3 (adc_data_3),
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.adc_wr_en(adc_valid),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.adc_valid_2 (adc_valid_2),
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.adc_valid_3 (adc_valid_3),
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.adc_enable_0 (adc_enable_0),
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.adc_enable_1 (adc_enable_1),
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.adc_enable_2 (adc_enable_2),
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.adc_enable_3 (adc_enable_3),
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.adc_dovf (adc_dovf),
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.adc_dovf_0 (adc_dovf_0),
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.adc_dovf_1 (adc_dovf_1),
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.adc_dovf_2 (adc_dovf_2),
|
|
.adc_dovf_3 (adc_dovf_3),
|
|
.gt_rx_data (gt_rx_data),
|
|
.gt_rx_sof (gt_rx_sof),
|
|
.gt_rx_data_0 (gt_rx_data_0),
|
|
.gt_rx_sof_0(gt_rx_sof_0),
|
|
.gt_rx_data_1 (gt_rx_data_1),
|
|
.gt_rx_sof_1(gt_rx_sof_1),
|
|
.gt_rx_data_2 (gt_rx_data_2),
|
|
.gt_rx_sof_2(gt_rx_sof_2),
|
|
.gt_rx_data_3 (gt_rx_data_3),
|
|
.gt_rx_sof_3(gt_rx_sof_3),
|
|
.hdmi_data (hdmi_data),
|
|
.hdmi_data_e (hdmi_data_e),
|
|
.hdmi_hsync (hdmi_hsync),
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
.hdmi_vsync (hdmi_vsync),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_09 (1'b0),
|
|
.ps_intr_10 (1'b0),
|
|
.ps_intr_11 (1'b0),
|
|
.rx_data_n (rx_data_n),
|
|
.rx_data_p (rx_data_p),
|
|
.rx_ref_clk (rx_ref_clk),
|
|
.rx_sync (rx_sync),
|
|
.rx_sysref (rx_sysref),
|
|
.spdif (spdif),
|
|
.spi_clk_i (spi_clk),
|
|
.spi_clk_o (spi_clk),
|
|
.spi_csn_i (spi_csn),
|
|
.spi_csn_o (spi_csn),
|
|
.spi_sdi_i (spi_miso),
|
|
.spi_sdo_i (spi_mosi),
|
|
.spi_sdo_o (spi_mosi));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|