59 lines
6.1 KiB
Plaintext
59 lines
6.1 KiB
Plaintext
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# fmcadc4
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set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
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set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
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set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[0]] ; ## A14 FMC_HPC_DP4_M2C_P
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set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[0]] ; ## A15 FMC_HPC_DP4_M2C_N
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set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[1]] ; ## A18 FMC_HPC_DP5_M2C_P
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set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[1]] ; ## A19 FMC_HPC_DP5_M2C_N
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set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[2]] ; ## B16 FMC_HPC_DP6_M2C_P
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set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[2]] ; ## B17 FMC_HPC_DP6_M2C_N
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set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[3]] ; ## B12 FMC_HPC_DP7_M2C_P
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set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[3]] ; ## B13 FMC_HPC_DP7_M2C_N
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set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[4]] ; ## A10 FMC_HPC_DP3_M2C_P
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set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[4]] ; ## A11 FMC_HPC_DP3_M2C_N
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set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[5]] ; ## C06 FMC_HPC_DP0_M2C_P
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set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[5]] ; ## C07 FMC_HPC_DP0_M2C_N
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set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[6]] ; ## A06 FMC_HPC_DP2_M2C_P
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set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[6]] ; ## A07 FMC_HPC_DP2_M2C_N
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set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[7]] ; ## A02 FMC_HPC_DP1_M2C_P
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set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[7]] ; ## A03 FMC_HPC_DP1_M2C_N
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set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports rx_sync_0_p] ; ## G15 FMC_HPC_LA12_P
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set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports rx_sync_0_n] ; ## G16 FMC_HPC_LA12_N
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set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_p] ; ## H10 FMC_HPC_LA04_P
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set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_n] ; ## H11 FMC_HPC_LA04_N
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set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9528_csn] ; ## G13 FMC_HPC_LA08_N
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set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ada4961_1a_csn] ; ## G09 FMC_HPC_LA03_P
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set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports ada4961_1b_csn] ; ## G10 FMC_HPC_LA03_N
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set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports ad9234_1_csn] ; ## H13 FMC_HPC_LA07_P
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set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports ada4961_2a_csn] ; ## C10 FMC_HPC_LA06_P
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set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports ada4961_2b_csn] ; ## C11 FMC_HPC_LA06_N
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set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports ad9234_2_csn] ; ## H14 FMC_HPC_LA07_N
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D18 FMC_HPC_LA13_N
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D17 FMC_HPC_LA13_P
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set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9528_rstn] ; ## D15 FMC_HPC_LA09_N
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports ad9528_status] ; ## D14 FMC_HPC_LA09_P
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set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fda] ; ## C14 FMC_HPC_LA10_P
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set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fdb] ; ## C15 FMC_HPC_LA10_N
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set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fda] ; ## H16 FMC_HPC_LA11_P
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set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fdb] ; ## H17 FMC_HPC_LA11_N
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# clocks
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create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
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create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc4_gt_rx_clk]
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create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
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create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
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create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
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set_clock_groups -asynchronous -group {rx_div_clk}
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set_clock_groups -asynchronous -group {fmc_dma_clk}
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set_clock_groups -asynchronous -group {pl_ddr_clk}
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set_clock_groups -asynchronous -group {pl_dma_clk}
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