Istvan Csomortani d13ff8df1e axi_dmac: In SDP mode REGCEB is connected to GND ... In newer version of Vivado (e.g. 2017.4) the REGCEB pin of the block ram macro is connected to ground. So the following false path became redundant.		2018-04-11 15:09:54 +03:00
..
bd	axi_dmac: post_propagate(): Handle mappings with multiple address segments	2017-04-19 13:47:02 +02:00
2d_transfer.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
Makefile	Make: Use $(MAKE) for recursive make commands	2018-03-07 07:40:19 +00:00
address_generator.v	axi_dmac: Fix some data width mismatches	2017-08-01 15:22:29 +02:00
axi_dmac.v	axi_dmac: Add limited TLAST support for streaming AXI source interface	2018-01-23 17:43:48 +01:00
axi_dmac_constr.sdc	axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them	2015-07-23 17:01:02 +03:00
axi_dmac_constr.ttcl	axi_dmac: In SDP mode REGCEB is connected to GND	2018-04-11 15:09:54 +03:00
axi_dmac_hw.tcl	axi_dmac: Control s_axis_user/fifo_wr_sync validity	2017-10-03 09:32:14 +01:00
axi_dmac_ip.tcl	axi_dmac: Include TLAST in AXIS slave port	2018-01-23 17:43:48 +01:00
axi_register_slice.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
data_mover.v	axi_dmac: Fix some data width mismatches	2017-08-01 15:22:29 +02:00
dest_axi_mm.v	axi_dmac: dest_axi_mm: Use fixed wstrb signal	2017-08-01 15:22:29 +02:00
dest_axi_stream.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
dest_fifo_inf.v	axi_dmac: Align the data_ready to data	2017-11-21 13:15:03 +00:00
inc_id.h	axi_dmac: Fix some data width mismatches	2017-08-01 15:22:29 +02:00
request_arb.v	axi_dmac: Add limited TLAST support for streaming AXI source interface	2018-01-23 17:43:48 +01:00
request_generator.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
resp.h	Added axi_dmac, axi_fifo and misc files in library	2014-03-06 18:16:02 +02:00
response_generator.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
response_handler.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
splitter.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
src_axi_mm.v	axi_dmac: Comment out unused src_response interface	2017-08-01 15:22:29 +02:00
src_axi_stream.v	axi_dmac: Add limited TLAST support for streaming AXI source interface	2018-01-23 17:43:48 +01:00
src_fifo_inf.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00