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pluto_hdl_adi/library/axi_ad9671
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AndreiGrozav 66823682b6 Add FPGA info parameters flow 
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
 		2019-03-30 11:26:11 +02:00
..
bd Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
Makefile library: Remove empty constraint files 2018-04-11 15:09:54 +03:00
axi_ad9671.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9671_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9671_hw.tcl Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9671_if.v util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
axi_ad9671_ip.tcl Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9671_pnmon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00