996d0fe8a4
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous to all other clocks in the system. This is a bit unfortunate as these constraints are not restricted to the axi_hdmi_tx, but affect all cores in the system, some of which might actually have timing constraints on CDC paths. The proper way to fix this is to add constraints for the axi_hdmi_tx core CDC paths. For now only mark the interface clock asynchronous to the HDMI clock, as this is easy to do and an improvement over the current situation, as other cores are no longer affected. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: