190 lines
6.2 KiB
ReStructuredText
190 lines
6.2 KiB
ReStructuredText
.. _git_repository:
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HDL Git repository
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===============================================================================
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All the HDL sources can be found in the following git repository:
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:git-hdl:`/`
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We assume that the user is familiar with `git <https://git-scm.com/>`__.
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Knows how to
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the repository, how to check its
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`status <https://git-scm.com/docs/git-status>`__ or how to
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`switch <https://git-scm.com/book/en/v2/Git-Branching-Basic-Branching-and-Merging>`__
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between branches.
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.. note::
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A basic git knowledge is required in order to work with these source files,
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if you do not have any, don't worry!
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There are a lot of great resources and tutorials about git all over the
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`web <http://lmgtfy.com/?q=git+tutorial>`__.
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If you want to pull down the sources as soon as possible, just do the
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following few steps:
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#. Install Git from `here <https://git-scm.com/>`__
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#. Open up Git bash, change your current directory to a place where you
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want to keep the hdl source
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#. Clone the repository using
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`these <https://help.github.com/articles/cloning-a-repository/>`__
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instructions
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Folder structure
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-------------------------------------------------------------------------------
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The root of the HDL repository has the following structure:
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.. code-block::
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.
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+-- .github
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+-- docs
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+-- library
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+-- projects
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+-- scripts
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+-- Makefile
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+-- README.md
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+-- LICENSE
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The repository is divided into 5 separate sections:
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- **.github** with all our automations regarding coding checks, GitHub actions
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- **docs** with our GitHubIO documentation and regmap source files
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- **library** with all the Analog Devices Inc. proprietary IP cores and
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hdl modules, which are required to build the projects
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- **projects** with all the currently supported projects
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- **scripts** with our environment scripts that set tools versions, etc.
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The file **.gitattributes** is used to properly `handle
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different <https://help.github.com/articles/dealing-with-line-endings/>`__
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line endings. And the **.gitignore** specifies intentionally untracked
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files that Git should ignore. The root **Makefile** can be used to build
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all the project of the repository. To learn more about hdl **Makefiles**
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visit the :ref:`Building & Generating programming files <build_hdl>` section.
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The projects are structured as follows
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block::
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.
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+-- docs
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+-- library
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+-- projects
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¦ +-- ad40xx_fmc
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¦ +-- ad4110
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¦ .
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¦ +-- common
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¦ +-- dac_fmc_ebz
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¦ ¦ +-- common
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¦ ¦ +-- a10soc
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¦ ¦ +-- vcu118
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¦ ¦ .
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¦ ¦ +-- zcu102
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¦ ¦ +-- Makefile
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¦ ¦ +-- Readme.md
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¦ .
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¦ +-- scripts
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¦ .
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¦ +-- Readme.md
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¦ +-- Makefile
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¦ +-- wiki_summary.sh
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+-- README.md
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Besides the project folders, there are two special folders inside the
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**/hdl/projects**:
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- **common**: This folder contains all the base designs, for all
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currently supported FPGA development boards. Be aware if you see your
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board on this list, it does not necessarily mean that you can use it
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with your FMC board.
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- **scripts**: In all cases, we are interacting with the development
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tools (Vivado/Quartus) using Tcl scripts. In this folder are defined
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all the custom Tcl processes, which are used to create a project,
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define the system and generate programming files for the FPGA.
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Inside a project folder, you can find folders with an FPGA carrier name
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(e.g. ZC706) which in general contains all the carrier board specific
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files, and a folder called **common** which contains the project
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specific files. If you can not find your FPGA board name in a project
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folder, that means your FPGA board with that particular FMC board is not
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supported.
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The library are structured as follows
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block::
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.
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+-- library
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¦ +-- ad463x_data_capture
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¦ +-- axi_ad3552r
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¦ +-- axi_ad4858
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¦ +-- axi_ad5766
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¦ +-- axi_ad7606x
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¦ +-- axi_ad7616
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¦ +-- axi_ad7768
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¦ +-- axi_ad777x
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¦ +-- axi_ad9122
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¦ .
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¦ +-- common
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¦ .
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¦ +-- interfaces
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¦ +-- jesd204
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¦ +-- scripts
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¦ .
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¦ +-- Makefile
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+-- projects
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+-- README.md
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The library folder contains all the IP cores and common modules. An IP,
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in general, contains Verilog files, which describe the hardware logic,
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constraint files, to ease timing closure, and Tcl scripts, which
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generate all the other files required for IP integration (\*_ip.tcl for
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Vivado and \*_hw.tcl for Quartus) .
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.. note::
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Regarding Vivado, all the IPs must be 'packed' before being used in a
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design.
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To find more information about how to build the libraries, please visit
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the :ref:`Building & Generating programming files
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<build_hdl>` section.
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Repository releases and branches
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-------------------------------------------------------------------------------
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The repository may contain multiple branches and tags. The
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:git-hdl:`master <master:>` branch
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is the development branch (latest sources, but not stable). If you check
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out this branch, some builds may fail. If you are not into any kind of
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experimentation, you should only check out one of the release branch.
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All our release branches have the following naming convention:
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**hdl\_**\ [year_of_release]\ **\_r**\ [1 or 2]. (e.g.
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:git-hdl:`hdl_2014_r2 <hdl_2014_r2:>`)
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ADI does two releases each year when all the projects get an update to
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support the latest tools and get additional new features. \*\* The
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master branch is always synchronized with the latest release.*\* If you
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are in doubt, ask us on :ez:`fpga`.
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.. note::
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You can find the release notes on the GitHub page of the
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repository:
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https://github.com/analogdevicesinc/hdl/releases
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The latest version of tools used on master can be found at:
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:git-hdl:`master:scripts/adi_env.tcl` (*required_vivado_version* and
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*required_quartus_version* variables). For Intel Quartus Standard, the version
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is specified in each project that uses it, depending on the carrier.
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