74 lines
2.4 KiB
Verilog
74 lines
2.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7616_maxis2wrfifo #(
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parameter DATA_WIDTH = 16) (
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input clk,
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input rstn,
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input sync_in,
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// m_axis interface
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input [DATA_WIDTH-1:0] m_axis_data,
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output reg m_axis_ready,
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input m_axis_valid,
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output reg m_axis_xfer_req,
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// write fifo interface
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output reg fifo_wr_en,
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output reg [DATA_WIDTH-1:0] fifo_wr_data,
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output reg fifo_wr_sync,
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input fifo_wr_xfer_req
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);
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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m_axis_ready <= 1'b0;
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m_axis_xfer_req <= 1'b0;
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fifo_wr_data <= 'b0;
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fifo_wr_en <= 1'b0;
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fifo_wr_sync <= 1'b0;
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end else begin
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m_axis_ready <= 1'b1;
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m_axis_xfer_req <= fifo_wr_xfer_req;
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fifo_wr_data <= m_axis_data;
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fifo_wr_en <= m_axis_valid;
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if (sync_in == 1'b1) begin
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fifo_wr_sync <= 1'b1;
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end else if ((m_axis_valid == 1'b1) &&
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(fifo_wr_sync == 1'b1)) begin
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fifo_wr_sync <= 1'b0;
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end
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end
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end
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endmodule
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