50 lines
1.7 KiB
Verilog
50 lines
1.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_b2g #(
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parameter DATA_WIDTH = 8) (
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input [DATA_WIDTH-1:0] din,
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output [DATA_WIDTH-1:0] dout);
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function [DATA_WIDTH-1:0] b2g;
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input [DATA_WIDTH-1:0] b;
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integer i;
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begin
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b2g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
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for (i = DATA_WIDTH-1; i > 0; i = i -1) begin
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b2g[i-1] = b[i] ^ b[i-1];
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end
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end
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endfunction
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assign dout = b2g(din);
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endmodule
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