123 lines
3.7 KiB
Verilog
123 lines
3.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Input must be RGB or CrYCb in that order, output is CrY/CbY
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module ad_ss_444to422 #(
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parameter CR_CB_N = 0,
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parameter DELAY_DATA_WIDTH = 16) (
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// 444 inputs
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input clk,
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input s444_de,
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input [DW:0] s444_sync,
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input [23:0] s444_data,
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// 422 outputs
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output reg [DW:0] s422_sync,
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output reg [15:0] s422_data);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal registers
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reg s444_de_d = 'd0;
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reg [DW:0] s444_sync_d = 'd0;
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reg [23:0] s444_data_d = 'd0;
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reg s444_de_2d = 'd0;
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reg [DW:0] s444_sync_2d = 'd0;
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reg [23:0] s444_data_2d = 'd0;
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reg s444_de_3d = 'd0;
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reg [DW:0] s444_sync_3d = 'd0;
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reg [23:0] s444_data_3d = 'd0;
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reg [ 7:0] cr = 'd0;
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reg [ 7:0] cb = 'd0;
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reg cr_cb_sel = 'd0;
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// internal wires
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wire [ 9:0] cr_s;
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wire [ 9:0] cb_s;
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// fill the data pipe lines, hold the last data on edges
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always @(posedge clk) begin
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s444_de_d <= s444_de;
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s444_sync_d <= s444_sync;
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if (s444_de == 1'b1) begin
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s444_data_d <= s444_data;
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end
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s444_de_2d <= s444_de_d;
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s444_sync_2d <= s444_sync_d;
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if (s444_de_d == 1'b1) begin
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s444_data_2d <= s444_data_d;
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end
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s444_de_3d <= s444_de_2d;
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s444_sync_3d <= s444_sync_2d;
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if (s444_de_2d == 1'b1) begin
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s444_data_3d <= s444_data_2d;
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end
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end
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// get the average 0.25*s(n-1) + 0.5*s(n) + 0.25*s(n+1)
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assign cr_s = {2'd0, s444_data_d[23:16]} +
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{2'd0, s444_data_3d[23:16]} +
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{1'd0, s444_data_2d[23:16], 1'd0};
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assign cb_s = {2'd0, s444_data_d[7:0]} +
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{2'd0, s444_data_3d[7:0]} +
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{1'd0, s444_data_2d[7:0], 1'd0};
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always @(posedge clk) begin
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cr <= cr_s[9:2];
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cb <= cb_s[9:2];
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if (s444_de_3d == 1'b1) begin
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cr_cb_sel <= ~cr_cb_sel;
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end else begin
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cr_cb_sel <= CR_CB_N;
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end
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end
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// 422 outputs
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always @(posedge clk) begin
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s422_sync <= s444_sync_3d;
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if (s444_de_3d == 1'b0) begin
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s422_data <= 'd0;
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end else if (cr_cb_sel == 1'b1) begin
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s422_data <= {cr, s444_data_3d[15:8]};
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end else begin
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s422_data <= {cb, s444_data_3d[15:8]};
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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