64 lines
2.3 KiB
Verilog
64 lines
2.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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/*
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* Helper module for synchronizing bit signals from one clock domain to another.
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* It uses the standard approach of 2 FF in series.
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* Note, that while the module allows to synchronize multiple bits at once it is
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* only able to synchronize multi-bit signals where at max one bit changes per
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* clock cycle (e.g. a gray counter).
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*/
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module sync_bits
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(
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input [NUM_OF_BITS-1:0] in,
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input out_resetn,
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input out_clk,
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output [NUM_OF_BITS-1:0] out
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);
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// Number of bits to synchronize
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parameter NUM_OF_BITS = 1;
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// Whether input and output clocks are asynchronous, if 0 the synchronizer will
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// be bypassed and the output signal equals the input signal.
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parameter ASYNC_CLK = 1;
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reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
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reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
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always @(posedge out_clk)
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begin
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if (out_resetn == 1'b0) begin
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cdc_sync_stage1 <= 'b0;
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cdc_sync_stage2 <= 'b0;
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end else begin
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cdc_sync_stage1 <= in;
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cdc_sync_stage2 <= cdc_sync_stage1;
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end
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end
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assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
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endmodule
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