482 lines
15 KiB
Verilog
482 lines
15 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_adc_channel #(
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// parameters
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parameter COMMON_ID = 6'h01,
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parameter CHANNEL_ID = 4'h0,
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0,
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parameter DCFILTER_DISABLE = 0,
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parameter IQCORRECTION_DISABLE = 0) (
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// adc interface
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input adc_clk,
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input adc_rst,
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output adc_enable,
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output adc_iqcor_enb,
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output adc_dcfilt_enb,
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output adc_dfmt_se,
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output adc_dfmt_type,
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output adc_dfmt_enable,
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output [15:0] adc_dcfilt_offset,
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output [15:0] adc_dcfilt_coeff,
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output [15:0] adc_iqcor_coeff_1,
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output [15:0] adc_iqcor_coeff_2,
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output [ 3:0] adc_pnseq_sel,
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output [ 3:0] adc_data_sel,
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input adc_pn_err,
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input adc_pn_oos,
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input adc_or,
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// user controls
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output up_usr_datatype_be,
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output up_usr_datatype_signed,
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output [ 7:0] up_usr_datatype_shift,
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output [ 7:0] up_usr_datatype_total_bits,
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output [ 7:0] up_usr_datatype_bits,
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output [15:0] up_usr_decimation_m,
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output [15:0] up_usr_decimation_n,
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input adc_usr_datatype_be,
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input adc_usr_datatype_signed,
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input [ 7:0] adc_usr_datatype_shift,
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input [ 7:0] adc_usr_datatype_total_bits,
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input [ 7:0] adc_usr_datatype_bits,
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input [15:0] adc_usr_decimation_m,
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input [15:0] adc_usr_decimation_n,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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// internal registers
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reg up_wack_int = 'd0;
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reg up_adc_lb_enb = 'd0;
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reg up_adc_pn_sel = 'd0;
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reg up_adc_iqcor_enb = 'd0;
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reg up_adc_dcfilt_enb = 'd0;
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reg up_adc_dfmt_se = 'd0;
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reg up_adc_dfmt_type = 'd0;
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reg up_adc_dfmt_enable = 'd0;
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reg up_adc_pn_type = 'd0;
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reg up_adc_enable = 'd0;
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reg up_adc_pn_err_int = 'd0;
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reg up_adc_pn_oos_int = 'd0;
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reg up_adc_or_int = 'd0;
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reg [15:0] up_adc_dcfilt_offset = 'd0;
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reg [15:0] up_adc_dcfilt_coeff = 'd0;
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reg [15:0] up_adc_iqcor_coeff_1 = 'd0;
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reg [15:0] up_adc_iqcor_coeff_2 = 'd0;
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reg [ 3:0] up_adc_pnseq_sel = 'd0;
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reg [ 3:0] up_adc_data_sel = 'd0;
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reg up_usr_datatype_be_int = 'd0;
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reg up_usr_datatype_signed_int = 'd0;
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reg [ 7:0] up_usr_datatype_shift_int = 'd0;
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reg [ 7:0] up_usr_datatype_total_bits_int = 'd0;
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reg [ 7:0] up_usr_datatype_bits_int = 'd0;
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reg [15:0] up_usr_decimation_m_int = 'd0;
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reg [15:0] up_usr_decimation_n_int = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0;
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reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;
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reg [ 3:0] up_adc_pnseq_sel_m = 'd0;
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reg [ 3:0] up_adc_data_sel_m = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_adc_pn_err_s;
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wire up_adc_pn_oos_s;
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wire up_adc_or_s;
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// 2's complement function
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function [15:0] sm2tc;
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input [15:0] din;
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reg [15:0] dp;
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reg [15:0] dn;
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reg [15:0] dout;
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begin
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dp = {1'b0, din[14:0]};
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dn = ~dp + 1'b1;
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dout = (din[15] == 1'b1) ? dn : dp;
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sm2tc = dout;
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end
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endfunction
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// up control/status
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assign up_adc_pn_err = up_adc_pn_err_int;
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assign up_adc_pn_oos = up_adc_pn_oos_int;
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assign up_adc_or = up_adc_or_int;
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assign up_usr_datatype_be = up_usr_datatype_be_int;
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assign up_usr_datatype_signed = up_usr_datatype_signed_int;
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assign up_usr_datatype_shift = up_usr_datatype_shift_int;
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assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int;
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assign up_usr_datatype_bits = up_usr_datatype_bits_int;
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assign up_usr_decimation_m = up_usr_decimation_m_int;
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assign up_usr_decimation_n = up_usr_decimation_n_int;
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// decode block select
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assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0;
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assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0;
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// processor write interface
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assign up_wack = up_wack_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack_int <= 'd0;
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up_adc_lb_enb <= 'd0;
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up_adc_pn_sel <= 'd0;
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end else begin
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up_wack_int <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_adc_lb_enb <= up_wdata[11];
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up_adc_pn_sel <= up_wdata[10];
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end
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end
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end
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generate
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if (IQCORRECTION_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_iqcor_enb <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_iqcor_enb <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_adc_iqcor_enb <= up_wdata[9];
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end
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end
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end
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end
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endgenerate
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generate
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if (DCFILTER_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_dcfilt_enb <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_dcfilt_enb <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_adc_dcfilt_enb <= up_wdata[8];
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end
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end
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end
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end
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endgenerate
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generate
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if (DATAFORMAT_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_dfmt_se <= 'd0;
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up_adc_dfmt_type <= 'd0;
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up_adc_dfmt_enable <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_dfmt_se <= 'd0;
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up_adc_dfmt_type <= 'd0;
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up_adc_dfmt_enable <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_adc_dfmt_se <= up_wdata[6];
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up_adc_dfmt_type <= up_wdata[5];
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up_adc_dfmt_enable <= up_wdata[4];
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end
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end
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end
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end
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endgenerate
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_pn_type <= 'd0;
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up_adc_enable <= 'd0;
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up_adc_pn_err_int <= 'd0;
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up_adc_pn_oos_int <= 'd0;
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up_adc_or_int <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_adc_pn_type <= up_wdata[1];
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up_adc_enable <= up_wdata[0];
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end
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if (up_adc_pn_err_s == 1'b1) begin
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up_adc_pn_err_int <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
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up_adc_pn_err_int <= up_adc_pn_err_int & ~up_wdata[2];
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end
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if (up_adc_pn_oos_s == 1'b1) begin
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up_adc_pn_oos_int <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
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up_adc_pn_oos_int <= up_adc_pn_oos_int & ~up_wdata[1];
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end
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if (up_adc_or_s == 1'b1) begin
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up_adc_or_int <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
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up_adc_or_int <= up_adc_or_int & ~up_wdata[0];
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end
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end
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end
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generate
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if (DCFILTER_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_dcfilt_offset <= 'd0;
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up_adc_dcfilt_coeff <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_dcfilt_offset <= 'd0;
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up_adc_dcfilt_coeff <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
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up_adc_dcfilt_offset <= up_wdata[31:16];
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up_adc_dcfilt_coeff <= up_wdata[15:0];
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end
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end
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end
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end
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endgenerate
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generate
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if (IQCORRECTION_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_iqcor_coeff_1 <= 'd0;
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up_adc_iqcor_coeff_2 <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_iqcor_coeff_1 <= 'd0;
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up_adc_iqcor_coeff_2 <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
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up_adc_iqcor_coeff_1 <= up_wdata[31:16];
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up_adc_iqcor_coeff_2 <= up_wdata[15:0];
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end
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end
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end
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end
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endgenerate
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_pnseq_sel <= 'd0;
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up_adc_data_sel <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
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up_adc_pnseq_sel <= up_wdata[19:16];
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up_adc_data_sel <= up_wdata[3:0];
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end
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end
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end
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generate
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if (USERPORTS_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_usr_datatype_be_int <= 'd0;
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up_usr_datatype_signed_int <= 'd0;
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up_usr_datatype_shift_int <= 'd0;
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up_usr_datatype_total_bits_int <= 'd0;
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up_usr_datatype_bits_int <= 'd0;
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up_usr_decimation_m_int <= 'd0;
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up_usr_decimation_n_int <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_usr_datatype_be_int <= 'd0;
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up_usr_datatype_signed_int <= 'd0;
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up_usr_datatype_shift_int <= 'd0;
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up_usr_datatype_total_bits_int <= 'd0;
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up_usr_datatype_bits_int <= 'd0;
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up_usr_decimation_m_int <= 'd0;
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up_usr_decimation_n_int <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
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up_usr_datatype_be_int <= up_wdata[25];
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up_usr_datatype_signed_int <= up_wdata[24];
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up_usr_datatype_shift_int <= up_wdata[23:16];
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up_usr_datatype_total_bits_int <= up_wdata[15:8];
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up_usr_datatype_bits_int <= up_wdata[7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
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up_usr_decimation_m_int <= up_wdata[31:16];
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up_usr_decimation_n_int <= up_wdata[15:0];
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end
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end
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end
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end
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endgenerate
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// processor read interface
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assign up_rack = up_rack_int;
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assign up_rdata = up_rdata_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack_int <= 'd0;
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up_rdata_int <= 'd0;
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end else begin
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up_rack_int <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[3:0])
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4'h0: up_rdata_int <= { 20'd0, up_adc_lb_enb, up_adc_pn_sel,
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up_adc_iqcor_enb, up_adc_dcfilt_enb,
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1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
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2'd0, up_adc_pn_type, up_adc_enable};
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4'h1: up_rdata_int <= { 29'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
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4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
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4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
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4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
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4'h8: up_rdata_int <= { 6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
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adc_usr_datatype_shift, adc_usr_datatype_total_bits,
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adc_usr_datatype_bits};
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4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n};
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default: up_rdata_int <= 0;
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endcase
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end else begin
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up_rdata_int <= 32'd0;
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end
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end
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end
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// change coefficients to 2's complements
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_iqcor_coeff_tc_1 <= 16'd0;
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up_adc_iqcor_coeff_tc_2 <= 16'd0;
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end else begin
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up_adc_iqcor_coeff_tc_1 <= sm2tc(up_adc_iqcor_coeff_1);
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up_adc_iqcor_coeff_tc_2 <= sm2tc(up_adc_iqcor_coeff_2);
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end
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end
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// data/pn sources
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_pnseq_sel_m <= 4'd0;
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up_adc_data_sel_m <= 4'd0;
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end else begin
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case ({up_adc_pn_type, up_adc_pn_sel})
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2'b10: up_adc_pnseq_sel_m <= 4'h1;
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2'b01: up_adc_pnseq_sel_m <= 4'h9;
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default: up_adc_pnseq_sel_m <= up_adc_pnseq_sel;
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|
endcase
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|
if (up_adc_lb_enb == 1'b1) begin
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|
up_adc_data_sel_m <= 4'h1;
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|
end else begin
|
|
up_adc_data_sel_m <= up_adc_data_sel;
|
|
end
|
|
end
|
|
end
|
|
|
|
// adc control & status
|
|
|
|
up_xfer_cntrl #(.DATA_WIDTH(78)) i_xfer_cntrl (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_data_cntrl ({ up_adc_iqcor_enb,
|
|
up_adc_dcfilt_enb,
|
|
up_adc_dfmt_se,
|
|
up_adc_dfmt_type,
|
|
up_adc_dfmt_enable,
|
|
up_adc_enable,
|
|
up_adc_dcfilt_offset,
|
|
up_adc_dcfilt_coeff,
|
|
up_adc_iqcor_coeff_tc_1,
|
|
up_adc_iqcor_coeff_tc_2,
|
|
up_adc_pnseq_sel_m,
|
|
up_adc_data_sel_m}),
|
|
.up_xfer_done (),
|
|
.d_rst (adc_rst),
|
|
.d_clk (adc_clk),
|
|
.d_data_cntrl ({ adc_iqcor_enb,
|
|
adc_dcfilt_enb,
|
|
adc_dfmt_se,
|
|
adc_dfmt_type,
|
|
adc_dfmt_enable,
|
|
adc_enable,
|
|
adc_dcfilt_offset,
|
|
adc_dcfilt_coeff,
|
|
adc_iqcor_coeff_1,
|
|
adc_iqcor_coeff_2,
|
|
adc_pnseq_sel,
|
|
adc_data_sel}));
|
|
|
|
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_data_status ({up_adc_pn_err_s,
|
|
up_adc_pn_oos_s,
|
|
up_adc_or_s}),
|
|
.d_rst (adc_rst),
|
|
.d_clk (adc_clk),
|
|
.d_data_status ({ adc_pn_err,
|
|
adc_pn_oos,
|
|
adc_or}));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|