69 lines
3.1 KiB
Verilog
Executable File
69 lines
3.1 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// too bad- we have to do this!
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`timescale 1ns/100ps
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module util_bsplit #(
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parameter CHANNEL_DATA_WIDTH = 1,
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parameter NUM_OF_CHANNELS = 8) (
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input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_0,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_1,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_2,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_3,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_4,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_5,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_6,
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output [(CHANNEL_DATA_WIDTH-1):0] split_data_7);
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localparam NUM_OF_CHANNELS_M = 9;
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// internal signals
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wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s;
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// extend and split
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assign data_s[((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):(NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)] = 'd0;
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assign data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] = data;
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assign split_data_0 = data_s[((CHANNEL_DATA_WIDTH*1)-1):(CHANNEL_DATA_WIDTH*0)];
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assign split_data_1 = data_s[((CHANNEL_DATA_WIDTH*2)-1):(CHANNEL_DATA_WIDTH*1)];
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assign split_data_2 = data_s[((CHANNEL_DATA_WIDTH*3)-1):(CHANNEL_DATA_WIDTH*2)];
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assign split_data_3 = data_s[((CHANNEL_DATA_WIDTH*4)-1):(CHANNEL_DATA_WIDTH*3)];
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assign split_data_4 = data_s[((CHANNEL_DATA_WIDTH*5)-1):(CHANNEL_DATA_WIDTH*4)];
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assign split_data_5 = data_s[((CHANNEL_DATA_WIDTH*6)-1):(CHANNEL_DATA_WIDTH*5)];
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assign split_data_6 = data_s[((CHANNEL_DATA_WIDTH*7)-1):(CHANNEL_DATA_WIDTH*6)];
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assign split_data_7 = data_s[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)];
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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