Istvan Csomortani 9afc871b70 a10gx: Optimise the base design ... Add a clock crossing bridge for the interfaces that runs on a different clock than the emif_user_clk. This way we can simplify the main interconnect, and prevent occasional timing violations.		2019-06-04 11:28:37 +03:00
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a10gx_system_assign.tcl	a10gx: Force all used tiles to high speed, in order to improve timing	2017-10-04 16:16:00 +01:00
a10gx_system_qsys.tcl	a10gx: Optimise the base design	2019-06-04 11:28:37 +03:00