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pluto_hdl_adi/library/jesd204/jesd204_rx
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Laszlo Nagy 8e0a45dea9 jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4 
Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 		2021-11-19 18:14:43 +02:00
..
bd jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
Makefile jesd204_rx: fixed makefile 2021-10-07 12:48:08 +03:00
align_mux.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
elastic_buffer.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
error_monitor.v jesd204_rx: 64b mode support for receive peripheral 2020-02-10 09:47:07 +02:00
jesd204_ilas_monitor.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_lane_latency_monitor.v jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4 2021-11-19 18:14:43 +02:00
jesd204_rx.v jesd20r_rx/jesd204_tx: Support for F=64 2021-07-27 11:31:19 +03:00
jesd204_rx_cgs.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_rx_constr.sdc jesd204: Intel: NP12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_constr.ttcl jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg 2021-03-22 10:55:00 +02:00
jesd204_rx_ctrl.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_rx_ctrl_64b.v jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure 2021-03-08 10:46:52 +02:00
jesd204_rx_frame_align.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_header.v jesd204_rx: 64b mode support for receive peripheral 2020-02-10 09:47:07 +02:00
jesd204_rx_hw.tcl adi_jesd204: Add support of 16 lanes 2021-07-27 10:28:48 +03:00
jesd204_rx_ip.tcl jesd204/jesd204_rx: Define tie off values for unused ports 2021-10-05 14:09:51 +03:00
jesd204_rx_lane.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_lane_64b.v jesd204_rx:64b: Remove reset 2021-03-08 10:46:52 +02:00
jesd204_rx_ooc.ttcl jesd204: Add out of context constraint file for link layer cores 2021-05-14 15:39:40 +03:00