214 lines
7.1 KiB
Verilog
214 lines
7.1 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module tx_tb;
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parameter VCD_FILE = "tx_tb.vcd";
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parameter NUM_LANES = 4;
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parameter NUM_LINKS = 2;
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parameter OCTETS_PER_FRAME = 4;
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parameter FRAMES_PER_MULTIFRAME = 32;
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`include "tb_base.v"
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reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
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reg [31:0] counter = 'h00;
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reg [31:0] tx_data = 'h00000000;
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wire tx_ready;
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wire tx_valid = 1'b1;
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wire [NUM_LANES-1:0] cfg_lanes_disable;
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wire [NUM_LINKS-1:0] cfg_links_disable;
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wire [9:0] cfg_octets_per_multiframe;
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wire [7:0] cfg_octets_per_frame;
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wire [7:0] device_cfg_lmfc_offset;
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wire [9:0] device_cfg_octets_per_multiframe;
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wire [7:0] device_cfg_octets_per_frame;
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wire [7:0] device_cfg_beats_per_multiframe;
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wire device_cfg_sysref_disable;
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wire device_cfg_sysref_oneshot;
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wire cfg_continuous_cgs;
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wire cfg_continuous_ilas;
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wire cfg_skip_ilas;
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wire [7:0] cfg_mframes_per_ilas;
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wire cfg_disable_char_replacement;
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wire cfg_disable_scrambler;
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wire tx_ilas_config_rd;
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wire [1:0] tx_ilas_config_addr;
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wire [32*NUM_LANES-1:0] tx_ilas_config_data;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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tx_data <= 'h00000000;
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end else if (tx_ready == 1'b1) begin
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tx_data <= tx_data + 1'b1;
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end
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end
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/* Generate independent SYNCs
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*
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* Each SYNC will be asserted/deasserted at different clock edges.
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* The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
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*/
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always @(posedge clk) begin
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counter <= counter + 1'b1;
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end
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genvar i;
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generate
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for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR
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always @(posedge clk) begin
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if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
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sync[i-1] <= 1'b0;
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end else begin
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sync[i-1] <= 1'b1;
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end
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end
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end
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endgenerate
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// DUT with static configuration
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jesd204_tx_static_config #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
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.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
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) i_cfg (
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.clk(clk),
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.cfg_lanes_disable(cfg_lanes_disable),
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.cfg_links_disable(cfg_links_disable),
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.cfg_octets_per_multiframe(cfg_octets_per_multiframe),
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.cfg_octets_per_frame(cfg_octets_per_frame),
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.cfg_continuous_cgs(cfg_continuous_cgs),
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.cfg_continuous_ilas(cfg_continuous_ilas),
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.cfg_skip_ilas(cfg_skip_ilas),
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.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(cfg_disable_char_replacement),
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.cfg_disable_scrambler(cfg_disable_scrambler),
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.device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
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.device_cfg_octets_per_frame(device_cfg_octets_per_frame),
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.device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
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.device_cfg_lmfc_offset(device_cfg_lmfc_offset),
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.device_cfg_sysref_disable(device_cfg_sysref_disable),
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.device_cfg_sysref_oneshot(device_cfg_sysref_oneshot),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data)
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);
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jesd204_tx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.ASYNC_CLK(0)
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) i_tx (
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.clk(clk),
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.reset(reset),
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.device_clk(clk),
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.device_reset(reset),
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.phy_data(),
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.phy_charisk(),
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.phy_header(),
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.sysref(sysref),
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.lmfc_edge(),
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.lmfc_clk(),
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.sync(sync),
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.tx_data({NUM_LANES{tx_data}}),
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.tx_ready(tx_ready),
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.tx_eof(),
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.tx_sof(),
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.tx_somf(),
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.tx_eomf(),
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.tx_valid(1'b1),
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.cfg_lanes_disable(cfg_lanes_disable),
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.cfg_links_disable(cfg_links_disable),
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.cfg_octets_per_multiframe(cfg_octets_per_multiframe),
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.cfg_octets_per_frame(cfg_octets_per_frame),
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.cfg_continuous_cgs(cfg_continuous_cgs),
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.cfg_continuous_ilas(cfg_continuous_ilas),
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.cfg_skip_ilas(cfg_skip_ilas),
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.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
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.cfg_disable_char_replacement(cfg_disable_char_replacement),
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.cfg_disable_scrambler(cfg_disable_scrambler),
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.device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
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.device_cfg_octets_per_frame(device_cfg_octets_per_frame),
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.device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
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.device_cfg_lmfc_offset(device_cfg_lmfc_offset),
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.device_cfg_sysref_disable(device_cfg_sysref_disable),
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.device_cfg_sysref_oneshot(device_cfg_sysref_oneshot),
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.ilas_config_rd(tx_ilas_config_rd),
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.ilas_config_addr(tx_ilas_config_addr),
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.ilas_config_data(tx_ilas_config_data),
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.ctrl_manual_sync_request (1'b0),
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.device_event_sysref_edge (),
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.device_event_sysref_alignment_error (),
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.status_sync (),
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.status_state (),
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.status_synth_params0(),
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.status_synth_params1(),
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.status_synth_params2()
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);
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endmodule
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