332 lines
9.9 KiB
Verilog
332 lines
9.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module axi_hdmi_tx #(
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parameter ID = 0,
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parameter CR_CB_N = 0,
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parameter DEVICE_TYPE = 0,
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parameter EMBEDDED_SYNC = 0,
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parameter OUT_CLK_POLARITY = 0) (
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// hdmi interface
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input hdmi_clk,
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output hdmi_out_clk,
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// 16-bit interface
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output hdmi_16_hsync,
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output hdmi_16_vsync,
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output hdmi_16_data_e,
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output [15:0] hdmi_16_data,
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output [15:0] hdmi_16_es_data,
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// 24-bit interface
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output hdmi_24_hsync,
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output hdmi_24_vsync,
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output hdmi_24_data_e,
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output [23:0] hdmi_24_data,
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// 36-bit interface
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output hdmi_36_hsync,
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output hdmi_36_vsync,
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output hdmi_36_data_e,
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output [35:0] hdmi_36_data,
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// vdma interface
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input vdma_clk,
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output vdma_fs,
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input vdma_fs_ret,
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input vdma_valid,
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input [63:0] vdma_data,
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output vdma_ready,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready);
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/* 0 = Launch on rising edge, 1 = Launch on falling edge */
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localparam XILINX_7SERIES = 0;
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localparam XILINX_ULTRASCALE = 1;
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localparam ALTERA_5SERIES = 16;
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// reset and clocks
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wire up_rstn;
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wire up_clk;
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wire hdmi_rst;
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wire vdma_rst;
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// internal signals
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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wire hdmi_csc_bypass_s;
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wire hdmi_ss_bypass_s;
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wire [ 1:0] hdmi_srcsel_s;
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wire [23:0] hdmi_const_rgb_s;
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wire [15:0] hdmi_hl_active_s;
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wire [15:0] hdmi_hl_width_s;
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wire [15:0] hdmi_hs_width_s;
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wire [15:0] hdmi_he_max_s;
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wire [15:0] hdmi_he_min_s;
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wire [15:0] hdmi_vf_active_s;
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wire [15:0] hdmi_vf_width_s;
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wire [15:0] hdmi_vs_width_s;
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wire [15:0] hdmi_ve_max_s;
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wire [15:0] hdmi_ve_min_s;
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wire [23:0] hdmi_clip_max_s;
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wire [23:0] hdmi_clip_min_s;
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wire hdmi_fs_toggle_s;
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wire [ 8:0] hdmi_raddr_g_s;
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wire hdmi_tpm_oos_s;
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wire hdmi_status_s;
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wire vdma_wr_s;
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wire [ 8:0] vdma_waddr_s;
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wire [47:0] vdma_wdata_s;
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wire vdma_fs_ret_toggle_s;
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wire [ 8:0] vdma_fs_waddr_s;
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wire vdma_ovf_s;
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wire vdma_unf_s;
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wire vdma_tpm_oos_s;
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// signal name changes
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// processor interface
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up_hdmi_tx i_up (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_csc_bypass (hdmi_csc_bypass_s),
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.hdmi_ss_bypass (hdmi_ss_bypass_s),
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.hdmi_srcsel (hdmi_srcsel_s),
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.hdmi_const_rgb (hdmi_const_rgb_s),
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.hdmi_hl_active (hdmi_hl_active_s),
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.hdmi_hl_width (hdmi_hl_width_s),
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.hdmi_hs_width (hdmi_hs_width_s),
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.hdmi_he_max (hdmi_he_max_s),
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.hdmi_he_min (hdmi_he_min_s),
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.hdmi_vf_active (hdmi_vf_active_s),
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.hdmi_vf_width (hdmi_vf_width_s),
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.hdmi_vs_width (hdmi_vs_width_s),
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.hdmi_ve_max (hdmi_ve_max_s),
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.hdmi_ve_min (hdmi_ve_min_s),
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.hdmi_clip_max (hdmi_clip_max_s),
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.hdmi_clip_min (hdmi_clip_min_s),
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.hdmi_status (hdmi_status_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_clk_ratio (32'd1),
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.vdma_clk (vdma_clk),
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.vdma_rst (vdma_rst),
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.vdma_ovf (vdma_ovf_s),
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.vdma_unf (vdma_unf_s),
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.vdma_tpm_oos (vdma_tpm_oos_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// vdma interface
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axi_hdmi_tx_vdma i_vdma (
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.hdmi_fs_toggle (hdmi_fs_toggle_s),
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.hdmi_raddr_g (hdmi_raddr_g_s),
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.vdma_clk (vdma_clk),
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.vdma_rst (vdma_rst),
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.vdma_fs (vdma_fs),
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.vdma_fs_ret (vdma_fs_ret),
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.vdma_valid (vdma_valid),
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.vdma_data (vdma_data),
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.vdma_ready (vdma_ready),
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.vdma_wr (vdma_wr_s),
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.vdma_waddr (vdma_waddr_s),
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.vdma_wdata (vdma_wdata_s),
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.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
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.vdma_fs_waddr (vdma_fs_waddr_s),
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.vdma_tpm_oos (vdma_tpm_oos_s),
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.vdma_ovf (vdma_ovf_s),
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.vdma_unf (vdma_unf_s));
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// hdmi interface
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axi_hdmi_tx_core #(
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.CR_CB_N(CR_CB_N),
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.EMBEDDED_SYNC(EMBEDDED_SYNC))
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i_tx_core (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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.hdmi_16_hsync (hdmi_16_hsync),
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.hdmi_16_vsync (hdmi_16_vsync),
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.hdmi_16_data_e (hdmi_16_data_e),
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.hdmi_16_data (hdmi_16_data),
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.hdmi_16_es_data (hdmi_16_es_data),
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.hdmi_24_hsync (hdmi_24_hsync),
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.hdmi_24_vsync (hdmi_24_vsync),
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.hdmi_24_data_e (hdmi_24_data_e),
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.hdmi_24_data (hdmi_24_data),
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.hdmi_36_hsync (hdmi_36_hsync),
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.hdmi_36_vsync (hdmi_36_vsync),
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.hdmi_36_data_e (hdmi_36_data_e),
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.hdmi_36_data (hdmi_36_data),
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.hdmi_fs_toggle (hdmi_fs_toggle_s),
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.hdmi_raddr_g (hdmi_raddr_g_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_status (hdmi_status_s),
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.vdma_clk (vdma_clk),
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.vdma_wr (vdma_wr_s),
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.vdma_waddr (vdma_waddr_s),
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.vdma_wdata (vdma_wdata_s),
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.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
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.vdma_fs_waddr (vdma_fs_waddr_s),
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.hdmi_csc_bypass (hdmi_csc_bypass_s),
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.hdmi_ss_bypass (hdmi_ss_bypass_s),
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.hdmi_srcsel (hdmi_srcsel_s),
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.hdmi_const_rgb (hdmi_const_rgb_s),
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.hdmi_hl_active (hdmi_hl_active_s),
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.hdmi_hl_width (hdmi_hl_width_s),
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.hdmi_hs_width (hdmi_hs_width_s),
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.hdmi_he_max (hdmi_he_max_s),
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.hdmi_he_min (hdmi_he_min_s),
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.hdmi_vf_active (hdmi_vf_active_s),
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.hdmi_vf_width (hdmi_vf_width_s),
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.hdmi_vs_width (hdmi_vs_width_s),
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.hdmi_ve_max (hdmi_ve_max_s),
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.hdmi_ve_min (hdmi_ve_min_s),
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.hdmi_clip_max (hdmi_clip_max_s),
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.hdmi_clip_min (hdmi_clip_min_s));
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// hdmi output clock
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generate
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if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
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ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
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.SR (1'b0),
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.D1 (~OUT_CLK_POLARITY),
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.D2 (OUT_CLK_POLARITY),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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if (DEVICE_TYPE == ALTERA_5SERIES) begin
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altddio_out #(.WIDTH(1)) i_clk_oddr (
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.aclr (1'b0),
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.aset (1'b0),
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.sclr (1'b0),
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.sset (1'b0),
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.oe (1'b1),
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.outclocken (1'b1),
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.datain_h (~OUT_CLK_POLARITY),
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.datain_l (OUT_CLK_POLARITY),
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.outclock (hdmi_clk),
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.oe_out (),
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.dataout (hdmi_out_clk));
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end
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if (DEVICE_TYPE == XILINX_7SERIES) begin
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ODDR #(.INIT(1'b0)) i_clk_oddr (
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.R (1'b0),
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.S (1'b0),
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.CE (1'b1),
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.D1 (~OUT_CLK_POLARITY),
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.D2 (OUT_CLK_POLARITY),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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