347 lines
15 KiB
Tcl
347 lines
15 KiB
Tcl
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if {[info exists DEBUG_BUILD] == 0} {
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set DEBUG_BUILD 1
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}
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set DISABLE_DMAC_DEBUG [expr !$DEBUG_BUILD]
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create_bd_port -dir I -from 15 -to 0 data_i
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create_bd_port -dir I -from 1 -to 0 trigger_i
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create_bd_port -dir O -from 15 -to 0 data_o
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create_bd_port -dir O -from 15 -to 0 data_t
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create_bd_port -dir O -from 1 -to 0 trigger_o
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create_bd_port -dir O -from 1 -to 0 trigger_t
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create_bd_port -dir I rx_clk
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create_bd_port -dir I rxiq
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create_bd_port -dir I -from 11 -to 0 rxd
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create_bd_port -dir I tx_clk
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create_bd_port -dir O txiq
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create_bd_port -dir O -from 11 -to 0 txd
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# AXI control interface and logic analyzer DMA (FCLK0): 27.8 MHz
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# Logic analyzer (FCLK2): 100 MHz
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# Converter DMA (FCLK3): 55.6 MHz
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK3_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 27.778
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 100.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ 55.556
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ad_connect logic_analyzer_clk_in sys_ps7/FCLK_CLK2
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ad_connect converter_dma_clk sys_ps7/FCLK_CLK3
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ad_ip_instance axi_logic_analyzer logic_analyzer
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ad_ip_instance util_var_fifo la_trigger_fifo
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ad_ip_parameter la_trigger_fifo CONFIG.DATA_WIDTH 16
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ad_ip_parameter la_trigger_fifo CONFIG.ADDRESS_WIDTH 13
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ad_ip_instance blk_mem_gen bram_la
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ad_ip_parameter bram_la CONFIG.use_bram_block {Stand_Alone}
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ad_ip_parameter bram_la CONFIG.Memory_Type {Simple_Dual_Port_RAM}
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ad_ip_parameter bram_la CONFIG.Assume_Synchronous_Clk {true}
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ad_ip_parameter bram_la CONFIG.Algorithm {Low_Power}
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ad_ip_parameter bram_la CONFIG.Use_Byte_Write_Enable {false}
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ad_ip_parameter bram_la CONFIG.Operating_Mode_A {NO_CHANGE}
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ad_ip_parameter bram_la CONFIG.Register_PortB_Output_of_Memory_Primitives {true}
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ad_ip_parameter bram_la CONFIG.Use_RSTA_Pin {false}
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ad_ip_parameter bram_la CONFIG.Port_B_Clock {100}
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ad_ip_parameter bram_la CONFIG.Port_B_Enable_Rate {100}
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ad_ip_parameter bram_la CONFIG.Write_Width_A {16}
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ad_ip_parameter bram_la CONFIG.Write_Width_B {16}
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ad_ip_parameter bram_la CONFIG.Read_Width_B {16}
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ad_ip_parameter bram_la CONFIG.Write_Depth_A {8192}
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ad_ip_instance axi_dmac logic_analyzer_dmac
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ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
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ad_ip_parameter logic_analyzer_dmac CONFIG.SYNC_TRANSFER_START true
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ad_ip_parameter logic_analyzer_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_dmac pattern_generator_dmac
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter pattern_generator_dmac CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter pattern_generator_dmac CONFIG.CYCLIC true
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ad_ip_parameter pattern_generator_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_ad9963 axi_ad9963
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ad_ip_parameter axi_ad9963 CONFIG.DAC_DATAPATH_DISABLE 1
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ad_ip_parameter axi_ad9963 CONFIG.ADC_USERPORTS_DISABLE 1
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ad_ip_parameter axi_ad9963 CONFIG.ADC_DATAFORMAT_DISABLE 1
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ad_ip_parameter axi_ad9963 CONFIG.ADC_DCFILTER_DISABLE 1
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ad_ip_parameter axi_ad9963 CONFIG.ADC_IQCORRECTION_DISABLE 0
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ad_ip_parameter axi_ad9963 CONFIG.ADC_SCALECORRECTION_ONLY 1
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ad_ip_instance util_var_fifo adc_trigger_fifo
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ad_ip_parameter adc_trigger_fifo CONFIG.DATA_WIDTH 32
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ad_ip_parameter adc_trigger_fifo CONFIG.ADDRESS_WIDTH 13
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ad_ip_instance blk_mem_gen bram_adc
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ad_ip_parameter bram_adc CONFIG.use_bram_block {Stand_Alone}
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ad_ip_parameter bram_adc CONFIG.Memory_Type {Simple_Dual_Port_RAM}
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ad_ip_parameter bram_adc CONFIG.Assume_Synchronous_Clk true
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ad_ip_parameter bram_adc CONFIG.Algorithm {Low_Power}
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ad_ip_parameter bram_adc CONFIG.Enable_32bit_Address false
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ad_ip_parameter bram_adc CONFIG.Use_Byte_Write_Enable false
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ad_ip_parameter bram_adc CONFIG.Operating_Mode_A {NO_CHANGE}
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ad_ip_parameter bram_adc CONFIG.Register_PortB_Output_of_Memory_Primitives true
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ad_ip_parameter bram_adc CONFIG.Use_RSTA_Pin {false}
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ad_ip_parameter bram_adc CONFIG.Port_B_Clock 100
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ad_ip_parameter bram_adc CONFIG.Port_B_Enable_Rate 100
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ad_ip_parameter bram_adc CONFIG.Write_Width_A 32
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ad_ip_parameter bram_adc CONFIG.Write_Width_B 32
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ad_ip_parameter bram_adc CONFIG.Read_Width_B 32
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ad_ip_parameter bram_adc CONFIG.Write_Depth_A 8192
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ad_ip_instance util_extract adc_trigger_extract
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# FIXME: Bring this back eventually
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#ad_ip_instance util_cpack util_cpack_ad9963
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#ad_ip_parameter util_cpack_ad9963 CONFIG.NUM_OF_CHANNELS 2
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#ad_ip_parameter util_cpack_ad9963 CONFIG.CHANNEL_DATA_WIDTH 16
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create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 ad9963_adc_concat
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ad_ip_instance axi_dmac ad9963_adc_dmac
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ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
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ad_ip_parameter ad9963_adc_dmac CONFIG.SYNC_TRANSFER_START true
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ad_ip_parameter ad9963_adc_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_dmac ad9963_dac_dmac_a
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.CYCLIC {true}
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ad_ip_parameter ad9963_dac_dmac_a CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_dmac ad9963_dac_dmac_b
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.MAX_BYTES_PER_BURST 128
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_DEST 16
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.CYCLIC {true}
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ad_ip_parameter ad9963_dac_dmac_b CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
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ad_ip_instance axi_adc_trigger adc_trigger
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ad_ip_instance axi_adc_decimate axi_adc_decimate
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ad_ip_instance axi_dac_interpolate axi_dac_interpolate
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ad_ip_instance proc_sys_reset logic_analyzer_reset
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ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_logic
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ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_converter
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ad_connect data_i logic_analyzer/data_i
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ad_connect trigger_i logic_analyzer/trigger_i
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ad_connect data_o logic_analyzer/data_o
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ad_connect data_t logic_analyzer/data_t
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ad_connect logic_analyzer_clk_in logic_analyzer/clk
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ad_connect logic_analyzer_clk logic_analyzer/clk_out
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ad_connect logic_analyzer_clk pattern_generator_dmac/fifo_rd_clk
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ad_connect logic_analyzer_clk la_trigger_fifo/clk
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ad_connect logic_analyzer_clk bram_la/clkb
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ad_connect logic_analyzer_clk bram_la/clka
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ad_connect logic_analyzer_clk logic_analyzer_dmac/fifo_wr_clk
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ad_connect logic_analyzer_clk logic_analyzer_reset/slowest_sync_clk
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ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn
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ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst
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ad_connect la_trigger_fifo/data_in logic_analyzer/adc_data
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ad_connect la_trigger_fifo/data_in_valid logic_analyzer/adc_valid
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ad_connect bram_la/addra la_trigger_fifo/addr_w
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ad_connect bram_la/dina la_trigger_fifo/din_w
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ad_connect bram_la/ena la_trigger_fifo/en_w
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ad_connect bram_la/wea la_trigger_fifo/wea_w
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ad_connect bram_la/addrb la_trigger_fifo/addr_r
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ad_connect bram_la/doutb la_trigger_fifo/dout_r
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ad_connect bram_la/enb la_trigger_fifo/en_r
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ad_connect logic_analyzer_dmac/fifo_wr_din la_trigger_fifo/data_out
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ad_connect logic_analyzer_dmac/fifo_wr_en la_trigger_fifo/data_out_valid
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ad_connect logic_analyzer/trigger_offset la_trigger_fifo/depth
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ad_connect logic_analyzer/trigger_out logic_analyzer_dmac/fifo_wr_sync
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ad_connect pattern_generator_dmac/fifo_rd_en logic_analyzer/dac_read
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ad_connect pattern_generator_dmac/fifo_rd_dout logic_analyzer/dac_data
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ad_connect pattern_generator_dmac/fifo_rd_valid logic_analyzer/dac_valid
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ad_connect axi_ad9963/adc_clk adc_trigger_fifo/clk
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#ad_connect axi_ad9963/adc_clk util_cpack_ad9963/adc_clk
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ad_connect axi_adc_decimate/adc_clk axi_ad9963/adc_clk
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ad_connect axi_adc_decimate/adc_rst axi_ad9963/adc_rst
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ad_connect adc_trigger_extract/clk axi_ad9963/adc_clk
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ad_connect ad9963_adc_dmac/fifo_wr_clk axi_ad9963/adc_clk
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ad_connect bram_adc/clka axi_ad9963/adc_clk
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ad_connect bram_adc/clkb axi_ad9963/adc_clk
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#ad_connect axi_ad9963/adc_rst util_cpack_ad9963/adc_rst
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ad_connect axi_ad9963/adc_rst adc_trigger_fifo/rst
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ad_connect axi_adc_decimate/adc_data_a axi_ad9963/adc_data_i
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ad_connect axi_adc_decimate/adc_data_b axi_ad9963/adc_data_q
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ad_connect axi_adc_decimate/adc_valid_a axi_ad9963/adc_valid_i
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ad_connect axi_adc_decimate/adc_valid_b axi_ad9963/adc_valid_q
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#ad_connect axi_ad9963/adc_enable_i util_cpack_ad9963/adc_enable_0
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#ad_connect adc_trigger/data_valid_a_trig util_cpack_ad9963/adc_valid_0
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#ad_connect adc_trigger/data_a_trig util_cpack_ad9963/adc_data_0
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#ad_connect axi_ad9963/adc_enable_q util_cpack_ad9963/adc_enable_1
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#ad_connect adc_trigger/data_valid_b_trig util_cpack_ad9963/adc_valid_1
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#ad_connect adc_trigger/data_b_trig util_cpack_ad9963/adc_data_1
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#ad_connect adc_trigger_fifo/data_in util_cpack_ad9963/adc_data
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#ad_connect adc_trigger_fifo/data_in_valid util_cpack_ad9963/adc_valid
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#ad_connect util_cpack_ad9963/adc_data adc_trigger_extract/data_in_trigger
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ad_connect adc_trigger_fifo/din_w bram_adc/dina
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ad_connect adc_trigger_fifo/en_w bram_adc/ena
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ad_connect adc_trigger_fifo/wea_w bram_adc/wea
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ad_connect adc_trigger_fifo/addr_w bram_adc/addra
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ad_connect bram_adc/addrb adc_trigger_fifo/addr_r
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ad_connect bram_adc/doutb adc_trigger_fifo/dout_r
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ad_connect bram_adc/enb adc_trigger_fifo/en_r
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ad_connect adc_trigger/data_a_trig ad9963_adc_concat/In0
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ad_connect adc_trigger/data_b_trig ad9963_adc_concat/In1
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ad_connect adc_trigger/data_valid_a_trig adc_trigger_fifo/data_in_valid
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ad_connect ad9963_adc_concat/dout adc_trigger_fifo/data_in
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ad_connect ad9963_adc_concat/dout adc_trigger_extract/data_in_trigger
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ad_connect adc_trigger_fifo/depth adc_trigger/trigger_offset
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ad_connect adc_trigger_fifo/data_out adc_trigger_extract/data_in
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ad_connect adc_trigger_fifo/data_out_valid adc_trigger_extract/data_valid
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ad_connect adc_trigger_extract/data_out ad9963_adc_dmac/fifo_wr_din
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ad_connect adc_trigger_extract/trigger_out ad9963_adc_dmac/fifo_wr_sync
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ad_connect adc_trigger_fifo/data_out_valid ad9963_adc_dmac/fifo_wr_en
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ad_connect axi_dac_interpolate/dac_clk axi_ad9963/dac_clk
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ad_connect axi_dac_interpolate/dac_rst axi_ad9963/dac_rst
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ad_connect axi_dac_interpolate/dac_valid_a axi_ad9963/dac_valid_i
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ad_connect axi_dac_interpolate/dac_valid_b axi_ad9963/dac_valid_q
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ad_connect axi_dac_interpolate/dac_int_data_a axi_ad9963/dac_data_i
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ad_connect axi_dac_interpolate/dac_int_data_b axi_ad9963/dac_data_q
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ad_connect ad9963_dac_dmac_a/fifo_rd_clk axi_ad9963/dac_clk
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ad_connect ad9963_dac_dmac_b/fifo_rd_clk axi_ad9963/dac_clk
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ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/fifo_rd_dout
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ad_connect axi_dac_interpolate/dac_int_valid_a ad9963_dac_dmac_a/fifo_rd_en
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ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/fifo_rd_dout
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ad_connect axi_dac_interpolate/dac_int_valid_b ad9963_dac_dmac_b/fifo_rd_en
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ad_connect /axi_ad9963/tx_data txd
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ad_connect /axi_ad9963/tx_iq txiq
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ad_connect /axi_ad9963/tx_clk tx_clk
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ad_connect /axi_ad9963/trx_data rxd
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ad_connect /axi_ad9963/trx_clk rx_clk
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ad_connect /axi_ad9963/trx_iq rxiq
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ad_connect adc_trigger/data_a axi_adc_decimate/adc_dec_data_a
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ad_connect adc_trigger/data_valid_a axi_adc_decimate/adc_dec_valid_a
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ad_connect adc_trigger/data_b axi_adc_decimate/adc_dec_data_b
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ad_connect adc_trigger/data_valid_b axi_adc_decimate/adc_dec_valid_b
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ad_connect adc_trigger/clk axi_ad9963/adc_clk
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ad_connect trigger_i adc_trigger/trigger_i
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ad_connect trigger_o adc_trigger/trigger_o
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ad_connect trigger_t adc_trigger/trigger_t
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ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out
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ad_connect axi_ad9963/adc_dovf ad9963_adc_dmac/fifo_wr_overflow
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ad_connect axi_ad9963/dac_dunf ad9963_dac_dmac_a/fifo_rd_underflow
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# interconnects
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#ad_cpu_interconnect 0x70000000 clk_generator
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ad_cpu_interconnect 0x70100000 logic_analyzer
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ad_cpu_interconnect 0x70200000 axi_ad9963
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ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac
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ad_cpu_interconnect 0x7C420000 pattern_generator_dmac
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ad_cpu_interconnect 0x7C440000 ad9963_adc_dmac
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ad_cpu_interconnect 0x7C460000 ad9963_dac_dmac_b
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ad_cpu_interconnect 0x7C480000 ad9963_dac_dmac_a
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ad_cpu_interconnect 0x7C4c0000 adc_trigger
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ad_cpu_interconnect 0x7C500000 axi_adc_decimate
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ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate
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# Logic analyzer DMA
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ad_connect sys_cpu_clk axi_rd_wr_combiner_logic/clk
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ad_connect sys_cpu_clk logic_analyzer_dmac/m_dest_axi_aclk
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ad_connect sys_cpu_clk pattern_generator_dmac/m_src_axi_aclk
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ad_connect logic_analyzer_dmac/m_dest_axi axi_rd_wr_combiner_logic/s_wr_axi
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ad_connect pattern_generator_dmac/m_src_axi axi_rd_wr_combiner_logic/s_rd_axi
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_rd_wr_combiner_logic/m_axi
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# Converter DMA
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ad_connect converter_dma_clk axi_rd_wr_combiner_converter/clk
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ad_connect converter_dma_clk ad9963_adc_dmac/m_dest_axi_aclk
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ad_connect converter_dma_clk ad9963_dac_dmac_a/m_src_axi_aclk
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ad_connect ad9963_adc_dmac/m_dest_axi axi_rd_wr_combiner_converter/s_wr_axi
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ad_connect ad9963_dac_dmac_a/m_src_axi axi_rd_wr_combiner_converter/s_rd_axi
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ad_mem_hp2_interconnect converter_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect converter_dma_clk axi_rd_wr_combiner_converter/m_axi
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# Only 16-bit we can run at a slower clock
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi
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# Map rd-wr combiner
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assign_bd_address [get_bd_addr_segs { \
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axi_rd_wr_combiner_converter/s_rd_axi/reg0 \
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axi_rd_wr_combiner_converter/s_wr_axi/reg0 \
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axi_rd_wr_combiner_logic/s_rd_axi/reg0 \
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axi_rd_wr_combiner_logic/s_wr_axi/reg0 \
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}]
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set_property range 512M [get_bd_addr_segs { \
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ad9963_dac_dmac_a/m_src_axi/SEG_axi_rd_wr_combiner_converter_reg0 \
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ad9963_adc_dmac/m_dest_axi/SEG_axi_rd_wr_combiner_converter_reg0 \
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pattern_generator_dmac/m_src_axi/SEG_axi_rd_wr_combiner_logic_reg0 \
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logic_analyzer_dmac/m_dest_axi/SEG_axi_rd_wr_combiner_logic_reg0 \
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}]
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ad_connect sys_cpu_resetn logic_analyzer_dmac/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn pattern_generator_dmac/m_src_axi_aresetn
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ad_connect sys_cpu_resetn ad9963_adc_dmac/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn ad9963_dac_dmac_a/m_src_axi_aresetn
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ad_connect sys_cpu_resetn ad9963_dac_dmac_b/m_src_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 logic_analyzer_dmac/irq
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ad_cpu_interrupt ps-12 mb-13 pattern_generator_dmac/irq
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ad_cpu_interrupt ps-10 mb-14 ad9963_adc_dmac/irq
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ad_cpu_interrupt ps-9 mb-15 ad9963_dac_dmac_a/irq
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ad_cpu_interrupt ps-8 mb-16 ad9963_dac_dmac_b/irq
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