9cd218eb90
In case of high precision devices with just a simple SPI interface for control and data, the effective data rate can be significatly lower than the SPI clock, and more importantly there isn't any relation between the two clock domain. The rate is defined by a SOT (start of transfer) generator, which initiates a SPI transfer. Taking the fact that the generator runs on system clock (100 MHz), and the device can require smaller rate (in kHz domain), the 7 bit dac_datarate register is just too small. Therefor increasing to 16 bit. |
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| Makefile | ||
| axi_ad5766.v | ||
| axi_ad5766_ip.tcl | ||
| up_ad5766_sequencer.v | ||