220 lines
9.2 KiB
Tcl
220 lines
9.2 KiB
Tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# TX parameters
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set TX_NUM_OF_LANES 4 ; # L
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set TX_NUM_OF_CONVERTERS 2 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
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($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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set dac_fifo_name axi_ad9152_fifo
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 2 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
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($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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set adc_fifo_name axi_ad9680_fifo
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set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9152_xcvr
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ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_ad9152_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_ad9152_xcvr CONFIG.TX_OR_RX_N 1
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adi_axi_jesd204_tx_create axi_ad9152_jesd $TX_NUM_OF_LANES
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adi_tpl_jesd204_tx_create axi_ad9152_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance util_upack2 axi_ad9152_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9152_dma
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_ad9152_dma CONFIG.ID 1
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ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr
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ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
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adi_tpl_jesd204_rx_create axi_ad9680_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9680_dma
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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if {$sys_zynq == 0 || $sys_zynq == 1} {
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_data_width $adc_fifo_address_width
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}
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# shared transceiver core
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ad_ip_instance util_adxcvr util_daq3_xcvr
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ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV_RATIO 1
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
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ad_ip_parameter util_daq3_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_daq3_xcvr CONFIG.TX_OUT_DIV 1
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ad_ip_parameter util_daq3_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
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ad_ip_parameter util_daq3_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
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ad_connect $sys_cpu_resetn util_daq3_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_daq3_xcvr/up_clk
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# reference clocks & resets
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create_bd_port -dir I tx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
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# connections (dac)
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ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1}
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_tpl_core/link_clk
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ad_connect axi_ad9152_jesd/tx_data axi_ad9152_tpl_core/link
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/clk
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ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_upack/reset
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ad_connect axi_ad9152_tpl_core/dac_valid_0 axi_ad9152_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect axi_ad9152_tpl_core/dac_enable_$i axi_ad9152_upack/enable_$i
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ad_connect axi_ad9152_tpl_core/dac_data_$i axi_ad9152_upack/fifo_rd_data_$i
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}
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if {$sys_zynq == 0 || $sys_zynq == 1} {
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ad_connect $sys_dma_clk axi_ad9152_fifo/dma_clk
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ad_connect $sys_dma_reset axi_ad9152_fifo/dma_rst
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ad_connect $sys_dma_clk axi_ad9152_dma/m_axis_aclk
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ad_connect $sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
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ad_connect axi_ad9152_fifo/bypass GND
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}
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
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ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
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# TODO: Add streaming AXI interface for DAC FIFO
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ad_connect axi_ad9152_upack/s_axis_valid VCC
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ad_connect axi_ad9152_upack/s_axis_ready axi_ad9152_fifo/dac_valid
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ad_connect axi_ad9152_upack/s_axis_data axi_ad9152_fifo/dac_data
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ad_connect axi_ad9152_tpl_core/dac_dunf axi_ad9152_fifo/dac_dunf
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ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
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ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
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ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
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ad_connect axi_ad9152_fifo/dma_valid axi_ad9152_dma/m_axis_valid
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ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
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# connections (adc)
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ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_tpl_core/link_clk
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ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl_core/link_sof
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ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl_core/link_data
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ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl_core/link_valid
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ad_connect axi_ad9680_tpl_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
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if {$sys_zynq == 0 || $sys_zynq == 1} {
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
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ad_connect $sys_dma_clk axi_ad9680_fifo/dma_clk
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ad_connect $sys_dma_clk axi_ad9680_dma/s_axis_aclk
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ad_connect $sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
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ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
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ad_connect axi_ad9680_tpl_core/adc_dovf axi_ad9680_fifo/adc_wovf
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}
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ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect axi_ad9680_tpl_core/adc_enable_$i axi_ad9680_cpack/enable_$i
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ad_connect axi_ad9680_tpl_core/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
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}
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
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ad_cpu_interconnect 0x44A04000 axi_ad9152_tpl_core
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ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
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ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl_core
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ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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if {$sys_zynq == 0 || $sys_zynq == 1} {
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ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_dma_clk axi_ad9152_dma/m_src_axi
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_ad9680_dma/m_dest_axi
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
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}
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# interrupts
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ad_cpu_interrupt ps-10 mb-15 axi_ad9152_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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