Laszlo Nagy 3cd203e9c7 scripts/adi_board.tcl: improvements for vcu128 DDR controller ... - allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus - some DDR controllers have an Axi Lite control interface, this creates a second address segment which causes issues, differentiate the memory segment from control registers segment		2021-11-19 18:08:16 +02:00
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adi_board.tcl	scripts/adi_board.tcl: improvements for vcu128 DDR controller	2021-11-19 18:08:16 +02:00
adi_env.tcl	scripts/adi_env.tcl: print in logs system variables are used	2020-05-20 19:07:23 +03:00
adi_intel_msg.tcl	adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10	2020-09-25 12:56:14 +03:00
adi_make.tcl	adi_make: Update bin build flow for 2020.1 tools	2021-08-10 17:44:30 +03:00
adi_make_boot_bin.tcl	adi_make: Update bin build flow for 2020.1 tools	2021-08-10 17:44:30 +03:00
adi_pd.tcl	sysid: Make sure gitbranch_string is always declared	2021-03-24 13:34:32 +02:00
adi_project_intel.tcl	scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl	2021-10-02 12:34:10 +03:00
adi_project_xilinx.tcl	projects/common/vcu128: Initial VCU128 support	2021-11-19 18:08:16 +02:00
adi_tquest.tcl	adi_tquest: Improve the timing report generation	2018-08-08 15:09:19 +03:00
adi_xilinx_msg.tcl	adi_xilinx_msg: Downgrade Synth 8-2490	2021-01-15 13:50:53 +02:00
project-intel.mk	Make system: Be explicit in license that cover the make/build system	2021-09-16 16:50:53 +03:00
project-toplevel.mk	Make system: Be explicit in license that cover the make/build system	2021-09-16 16:50:53 +03:00
project-xilinx.mk	scripts: Add logic for vivado version check	2021-10-12 14:34:11 +03:00