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AndreiGrozav 47fa86cfd6 axi_logic_analyzer: Optimize the input data path 
The input data path has a delay section that compensates for the ADC path delay.
By using a Dynamic Shift Registers coding style we can improve/change the
resource utilization on m2k:
          Before     After    Resources
LUT       10097      10048     48 (0.28%)
LUTRAM    516        540      -24 (-0.4%)
FF        15285      14803    482 (1.37%)
 		2020-08-13 07:01:19 +03:00
..
Makefile Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_logic_analyzer.v axi_logic_analyzer: Optimize the input data path 2020-08-13 07:01:19 +03:00
axi_logic_analyzer_constr.xdc axi_logic_analyzer: Optimize the input data path 2020-08-13 07:01:19 +03:00
axi_logic_analyzer_ip.tcl library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_logic_analyzer_reg.v axi_logic_analyzer: Auto sync to ADC path 2020-08-13 07:01:19 +03:00
axi_logic_analyzer_trigger.v axi_logic_analyzer: Add trigger disable condition 2020-06-26 10:47:15 +03:00