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Istvan Csomortani 9f7fff2d2f axi_ad9361/tdd: Add new control signals to the TDD data flow control logic 
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
 		2015-07-16 14:10:49 +03:00
library axi_ad9361/tdd: Add new control signals to the TDD data flow control logic 2015-07-16 14:10:49 +03:00
projects daq2/a10gx- axi_jesd_xcvr sysref name changes 2015-07-15 15:59:52 -04:00
.gitattributes Add .gitattributes file 2015-06-26 11:07:10 +02:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README: Update Vivado version number, 2014.4.1 is the new supported version 2015-03-03 09:48:13 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.4.1
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga