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Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>		2023-07-11 15:17:41 +03:00
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common	ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter	2023-03-29 21:33:33 +03:00
zed	Add/edit copyright and license for .v, .sv files	2023-07-11 15:17:41 +03:00
Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
Readme.md	ad7606x_fmc: Initial commit	2023-01-12 17:38:14 +02:00

Readme.md

AD7606X-FMC HDL Project

Here are some pointers to help you:

EVAL-AD7606B Product Page
EVAL-AD7606C-16/18 Product Page
Parts : AD7606B 8 Channels, 16-bit, 800 kSPS Bipolar Input, Simultaneous sampling ADC
Parts : AD7606C-16 8 Channels, 16-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC
Parts : AD7606B 8 Channels, 18-bit, 1 MSPS Bipolar Input, Simultaneous sampling ADC
Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmcz
HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl
Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl

Building, Generating Bit Files

IMPORTANT: Set AD7606X device model, ADC Read Mode option and external clock option

How to use over-writable parameters from the environment:

hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=0 SIMPLE_STATUS_CRC=0
DEV_CONFIG  - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.