c29c092bdc
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC. The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal. If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS. If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS. The VADJ voltage should be set to 1.8V. Signed-off-by: PopPaul2021 <Paul.Pop@analog.com> |
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| .. | ||
| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||