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laurent-19 b03d985e9d projects: Update readmes all projects initial version 
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 		2023-07-31 09:35:39 +03:00
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ccbob_cmos Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
ccbob_lvds Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
ccpackrf_lvds Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
common Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
Makefile library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
Readme.md projects: Update readmes all projects initial version 2023-07-31 09:35:39 +03:00

Readme.md

ADRV9364Z7020 SDR SOM

This folder contains the ADRV9364Z7020 SOM projects for each of the carrier boards.

Supported SOM & Carriers

Directory Description
ccbob_cmos ADRV9364Z7020-SOM (CMOS Mode) + ADRV1CRR-BOB
ccbob_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-BOB
ccpackrf_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-PACKRF
ccusb_lvds ADRV9364Z7020-SOM (LVDS Mode) + ADRV1CRR-USB

Board Design Files (Vivado IPI)

Directory/File Description
common/ADRV9364Z7020_bd.tcl ADRV9364Z7020-SOM board design file.
common/ccbob_bd.tcl carrier, break out board design file.
common/ccpackrf_bd.tcl carrier, packrf board design file.
common/ccusb_bd.tcl carrier, usb board design file.

FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.

Board Constraint Files (pin-out & io-standard)

Directory/File Description
common/ADRV9364Z7020_constr.xdc ADRV9364Z7020-SOM base constraints file.
common/ADRV9364Z7020_constr_cmos.xdc ADRV9364Z7020-SOM CMOS mode constraints file.
common/ADRV9364Z7020_constr_lvds.xdc ADRV9364Z7020-SOM LVDS mode constraints file.
common/ccbob_constr.xdc carrier, break out board constraints file.
common/ccpackrf_constr.xdc carrier, packrf board constraints file.
common/ccusb_constr.xdc carrier, usb board constraints file.

FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.

Building, Generating Bit Files (easy & efficient method)

[some-directory]> git clone -b dev git@github.com:analogdevicesinc/hdl.git
[some-directory]> make -C hdl/projects/adrv9364z7020/ccbob_cmos

Building, Generating Elf Files (easy & efficient method)

[some-directory]> git clone -b dev git@github.com:analogdevicesinc/no-OS.git
[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos

Running, a quick test (easy & efficient method)

[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos run

ADRV9364Z7020 HDL Project

Here are some pointers to help you: