213 lines
7.2 KiB
Tcl
213 lines
7.2 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# JESD204 TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 2 ; # M
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set TX_SAMPLES_PER_FRAME 2 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr [expr $TX_NUM_OF_LANES * 32 ] / \
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[expr $TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH]] ; # L * 32 / (M * N)
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# JESD204 RX parameters
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set RX_NUM_OF_LANES 8 ; # L
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set RX_NUM_OF_CONVERTERS 1 ; # M
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set RX_SAMPLES_PER_FRAME 4 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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# Data path FIFO attributes
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set adc_fifo_name axi_ad9625_fifo
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set adc_data_width 256
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set adc_dma_data_width 64
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set dac_fifo_name axi_ad9162_fifo
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set dac_data_width 256
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set dac_dma_data_width 256
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# DAC FIFO bypass
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create_bd_port -dir I dac_fifo_bypass
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9162_xcvr [list \
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NUM_OF_LANES 8 \
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QPLL_ENABLE 1 \
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TX_OR_RX_N 1 \
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]
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adi_axi_jesd204_tx_create axi_ad9162_jesd 8
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adi_tpl_jesd204_tx_create axi_ad9162_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance util_upack2 util_ad9162_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9162_dma [list \
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DMA_TYPE_SRC 0 \
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DMA_TYPE_DEST 1 \
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ID 1 \
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AXI_SLICE_SRC 0 \
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AXI_SLICE_DEST 0 \
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DMA_LENGTH_WIDTH 24 \
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DMA_2D_TRANSFER 0 \
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CYCLIC 0 \
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DMA_DATA_WIDTH_SRC 256 \
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DMA_DATA_WIDTH_DEST 256 \
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]
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9625_xcvr [list \
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NUM_OF_LANES 8 \
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QPLL_ENABLE 0 \
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TX_OR_RX_N 0 \
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]
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adi_tpl_jesd204_rx_create axi_ad9625_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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adi_axi_jesd204_rx_create axi_ad9625_jesd 8
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ad_ip_instance axi_dmac axi_ad9625_dma [list \
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DMA_TYPE_SRC 1 \
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DMA_TYPE_DEST 0 \
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ID 0 \
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AXI_SLICE_SRC 0 \
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AXI_SLICE_DEST 0 \
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SYNC_TRANSFER_START 0 \
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DMA_LENGTH_WIDTH 24 \
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DMA_2D_TRANSFER 0 \
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CYCLIC 0 \
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DMA_DATA_WIDTH_SRC 64 \
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DMA_DATA_WIDTH_DEST 64 \
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]
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
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# shared transceiver core
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ad_ip_instance util_adxcvr util_fmcomms11_xcvr [list \
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QPLL_FBDIV 0x120 \
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CPLL_FBDIV 4 \
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TX_NUM_OF_LANES 8 \
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TX_CLK25_DIV 7 \
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RX_NUM_OF_LANES 8 \
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RX_CLK25_DIV 7 \
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RX_DFE_LPM_CFG 0x0904 \
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RX_CDR_CFG 0x03000023ff10400020 \
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]
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# reference clocks & resets
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create_bd_port -dir I tx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_*
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ad_connect $sys_cpu_resetn util_fmcomms11_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_fmcomms11_xcvr/up_clk
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# connections (dac)
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ad_xcvrcon util_fmcomms11_xcvr axi_ad9162_xcvr axi_ad9162_jesd {0 1 2 3 7 4 6 5}
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ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_core/link_clk
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ad_connect axi_ad9162_jesd/tx_data axi_ad9162_core/link
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ad_connect util_fmcomms11_xcvr/tx_out_clk_0 util_ad9162_upack/clk
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ad_connect axi_ad9162_jesd_rstgen/peripheral_reset util_ad9162_upack/reset
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ad_connect axi_ad9162_core/dac_valid_0 util_ad9162_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect util_ad9162_upack/fifo_rd_data_$i axi_ad9162_core/dac_data_$i
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ad_connect axi_ad9162_core/dac_enable_$i util_ad9162_upack/enable_$i
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}
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ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk
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ad_connect axi_ad9162_jesd_rstgen/peripheral_reset axi_ad9162_fifo/dac_rst
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ad_connect $sys_cpu_clk axi_ad9162_fifo/dma_clk
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ad_connect $sys_cpu_reset axi_ad9162_fifo/dma_rst
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ad_connect $sys_cpu_clk axi_ad9162_dma/m_axis_aclk
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ad_connect $sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn
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ad_connect util_ad9162_upack/s_axis_valid VCC
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ad_connect util_ad9162_upack/s_axis_ready axi_ad9162_fifo/dac_valid
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ad_connect util_ad9162_upack/s_axis_data axi_ad9162_fifo/dac_data
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ad_connect axi_ad9162_core/dac_dunf axi_ad9162_fifo/dac_dunf
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ad_connect axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req
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ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready
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ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data
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ad_connect axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid
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ad_connect axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
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ad_connect dac_fifo_bypass axi_ad9162_fifo/bypass
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# connections (adc)
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ad_xcvrcon util_fmcomms11_xcvr axi_ad9625_xcvr axi_ad9625_jesd {0 1 2 3 7 4 6 5}
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ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_core/link_clk
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ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/link_sof
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ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/link_data
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ad_connect axi_ad9625_jesd/rx_data_tvalid axi_ad9625_core/link_valid
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ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
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ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
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ad_connect axi_ad9625_core/adc_valid_0 axi_ad9625_fifo/adc_wr
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ad_connect axi_ad9625_core/adc_data_0 axi_ad9625_fifo/adc_wdata
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ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk
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ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk
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ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
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ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
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ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
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ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
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ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
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ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9162_xcvr
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ad_cpu_interconnect 0x44A00000 axi_ad9162_core
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ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9162_dma
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ad_cpu_interconnect 0x44A50000 axi_ad9625_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9625_core
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ad_cpu_interconnect 0x44AA0000 axi_ad9625_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9625_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9625_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9162_dma/m_src_axi
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9625_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-10 mb-15 axi_ad9162_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_ad9625_jesd/irq
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ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
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ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
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