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Lars-Peter Clausen a0e30a2211 util_axis_fifo: Improve clock gating of registers and BRAM 
Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-04-18 12:17:39 +02:00
..
altera all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad6676 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad7616 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9122 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9144 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9152 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9162 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9234 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9250 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9265 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9361 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9371 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9434 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9467 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9625 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9643 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9652 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9671 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9680 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9684 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9739a all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9963 axi_ad9963: Allow to disable the IDELAYs on the ADC data path 2017-04-18 12:17:39 +02:00
axi_adc_decimate axi_adc_decimate: Make adc_reset external 2017-04-18 12:17:39 +02:00
axi_adc_trigger axi_adc_trigger: Temporarily disable trigger reporting in register map 2017-04-18 12:17:39 +02:00
axi_clkgen all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_dac_interpolate axi_dac_interpolate: Make dac_reset external 2017-04-18 12:17:39 +02:00
axi_dmac axi_dmac: Propagate awlen/arlen width through the core 2017-03-30 17:19:38 +02:00
axi_generic_adc updated makefiles 2016-12-09 23:06:41 +02:00
axi_gpreg all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_hdmi_rx all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_hdmi_tx all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_i2s_adi library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_intr_monitor updated makefiles 2016-12-09 23:06:41 +02:00
axi_logic_analyzer library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_mc_controller library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_mc_current_monitor library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_mc_speed library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_rd_wr_combiner Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface 2017-04-18 12:17:39 +02:00
axi_spdif_rx library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_spdif_tx library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_usb_fx3 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
cn0363 updated makefiles 2016-12-09 23:06:41 +02:00
common up_dac_common: Allow to disable GPIO registers 2017-04-18 12:17:39 +02:00
cordic_demod updated makefiles 2016-12-09 23:06:41 +02:00
interfaces interfaces- remove channel based pll reset 2016-11-22 11:34:29 -05:00
prcfg all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
scripts adi_ip- remove adi_ip_constraints 2017-04-02 10:42:51 -04:00
spi_engine spi_engine: Fix CMD_FIFO_VALID generation 2017-04-12 14:57:22 +02:00
util_adcfifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_axis_fifo util_axis_fifo: Improve clock gating of registers and BRAM 2017-04-18 12:17:39 +02:00
util_axis_resize updated makefiles 2016-12-09 23:06:41 +02:00
util_bsplit all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_ccat all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_clkdiv library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
util_cpack all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_dacfifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_extract all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_fir_dec util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero 2017-03-09 16:33:17 +02:00
util_fir_int util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input 2017-03-08 14:29:26 +02:00
util_gmii_to_rgmii all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_i2c_mixer updated makefiles 2016-12-09 23:06:41 +02:00
util_mfifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_pmod_adc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_pmod_fmeter all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_rfifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_sigma_delta_spi updated makefiles 2016-12-09 23:06:41 +02:00
util_tdd_sync all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_upack all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_var_fifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_wfifo all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
xilinx ad_lvds_in: Allow to disable IDELAY 2017-04-18 12:17:39 +02:00
Makefile Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface 2017-04-18 12:17:39 +02:00