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Istvan Csomortani a1539a62b7 avl_dacfifo: Integrate util_delay into dac_xfer_out path 
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
 		2017-05-25 15:12:13 +03:00
library avl_dacfifo: Integrate util_delay into dac_xfer_out path 2017-05-25 15:12:13 +03:00
projects m2k: Add scale correction option. Update parameters 2017-05-24 15:59:24 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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