71 lines
2.0 KiB
Verilog
71 lines
2.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_cmos_clk #(
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parameter DEVICE_TYPE = 0) (
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input rst,
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output locked,
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input clk_in,
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output clk);
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// instantiations
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generate
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if (DEVICE_TYPE == 0) begin
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alt_clk i_clk (
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.rst (rst),
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.refclk (clk_in),
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.outclk_0 (clk),
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.locked (locked));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == 1) begin
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altera_pll #(
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.reference_clock_frequency("250.0 MHz"),
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.operation_mode("source synchronous"),
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.number_of_clocks(1),
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.output_clock_frequency0("0 MHz"),
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.phase_shift0("0"))
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i_clk (
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.rst (rst),
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.refclk (clk_in),
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.outclk (clk),
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.fboutclk (),
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.fbclk (1'b0),
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.locked (locked));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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