120 lines
4.0 KiB
Verilog
120 lines
4.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// A simple asymetric memory. The write and read memory space must have the same size.
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// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
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`timescale 1ns/100ps
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module ad_mem_asym #(
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// parameters
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parameter A_ADDRESS_WIDTH = 8,
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parameter A_DATA_WIDTH = 256,
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parameter B_ADDRESS_WIDTH = 10,
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parameter B_DATA_WIDTH = 64) (
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// write interface
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input clka,
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input wea,
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input [A_ADDRESS_WIDTH-1:0] addra,
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input [A_DATA_WIDTH-1:0] dina,
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// read interface
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input clkb,
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input [B_ADDRESS_WIDTH-1:0] addrb,
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output [B_DATA_WIDTH-1:0] doutb);
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// broken altera-hdl-inference, direct instantiation
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altera_syncram #(
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.lpm_type ("altera_syncram"),
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.operation_mode ("DUAL_PORT"),
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.ram_block_type ("M20K"),
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.widthad_a (A_ADDRESS_WIDTH),
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.width_a (A_DATA_WIDTH),
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.numwords_a (2**A_ADDRESS_WIDTH),
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.widthad_b (B_ADDRESS_WIDTH),
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.width_b (B_DATA_WIDTH),
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.numwords_b (2**B_ADDRESS_WIDTH),
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.intended_device_family ("Arria 10"),
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.clock_enable_input_a ("BYPASS"),
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.clock_enable_input_b ("BYPASS"),
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.clock_enable_output_b ("BYPASS"),
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.address_aclr_b ("NONE"),
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.outdata_aclr_b ("NONE"),
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.outdata_sclr_b ("NONE"),
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.address_reg_b ("CLOCK1"),
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.outdata_reg_b ("CLOCK1"),
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.power_up_uninitialized ("FALSE"),
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.width_byteena_a (1))
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i_alt_mem (
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.aclr0 (1'b0),
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.clock0 (clka),
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.address_a (addra),
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.wren_a (wea),
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.data_a (dina),
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.rden_a (1'b1),
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.q_a (),
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.aclr1 (1'b0),
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.clock1 (clkb),
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.address_b (addrb),
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.wren_b (1'b0),
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.data_b ({B_DATA_WIDTH{1'd0}}),
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.rden_b (1'b1),
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.q_b (doutb),
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.address2_a (1'b1),
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.address2_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccencbypass (1'b0),
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.eccencparity (8'b0),
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.eccstatus (),
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.sclr (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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