80 lines
3.0 KiB
Verilog
80 lines
3.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_jesd_align (
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// jesd interface
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input rx_clk,
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input [ 3:0] rx_ip_sof,
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input [31:0] rx_ip_data,
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output reg rx_sof,
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output reg [31:0] rx_data);
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// internal registers
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reg [31:0] rx_ip_data_d = 'd0;
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reg [ 3:0] rx_ip_sof_hold = 'd0;
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reg rx_ip_sof_d = 'd0;
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// dword may contain more than one frame per clock
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always @(posedge rx_clk) begin
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rx_ip_data_d <= rx_ip_data;
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rx_ip_sof_d <= rx_ip_sof;
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if (rx_ip_sof != 4'h0) begin
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rx_ip_sof_hold <= rx_ip_sof;
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end
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rx_sof <= |rx_ip_sof_d;
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if (rx_ip_sof_hold[0] == 1'b1) begin
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rx_data <= rx_ip_data;
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end else if (rx_ip_sof_hold[1] == 1'b1) begin
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rx_data <= {rx_ip_data[ 7:0], rx_ip_data_d[31: 8]};
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end else if (rx_ip_sof_hold[2] == 1'b1) begin
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rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]};
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end else if (rx_ip_sof_hold[3] == 1'b1) begin
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rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]};
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end else begin
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rx_data <= 32'd0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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