229 lines
9.2 KiB
Verilog
Executable File
229 lines
9.2 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_upack #(
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parameter CHANNEL_DATA_WIDTH = 32,
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parameter NUM_OF_CHANNELS = 8) (
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// dac interface
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input dac_clk,
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input dac_enable_0,
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input dac_valid_0,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0,
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output upack_valid_0,
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input dac_enable_1,
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input dac_valid_1,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1,
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output upack_valid_1,
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input dac_enable_2,
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input dac_valid_2,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2,
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output upack_valid_2,
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input dac_enable_3,
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input dac_valid_3,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3,
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output upack_valid_3,
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input dac_enable_4,
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input dac_valid_4,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4,
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output upack_valid_4,
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input dac_enable_5,
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input dac_valid_5,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5,
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output upack_valid_5,
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input dac_enable_6,
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input dac_valid_6,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6,
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output upack_valid_6,
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input dac_enable_7,
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input dac_valid_7,
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output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7,
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output upack_valid_7,
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input dma_xfer_in,
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output reg dac_xfer_out,
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// fifo interface
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output reg dac_valid,
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output reg dac_sync,
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input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data);
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localparam NUM_OF_CHANNELS_M = 8;
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localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS;
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localparam CH_SCNT = CHANNEL_DATA_WIDTH/16;
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localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M;
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localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P;
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// internal registers
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reg [(M_WIDTH-1):0] dac_dsf_data = 'd0;
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reg [ 7:0] dac_dmx_enable = 'd0;
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reg xfer_valid_d1;
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reg xfer_valid_d2;
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reg xfer_valid_d3;
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reg xfer_valid_d4;
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reg xfer_valid_d5;
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// internal signals
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wire dac_valid_s;
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wire dac_dsf_valid_s[(NUM_OF_CHANNELS_M-1):0];
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wire dac_dsf_sync_s[(NUM_OF_CHANNELS_M-1):0];
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wire [(M_WIDTH-1):0] dac_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
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wire [(CH_SCNT-1):0] dac_dmx_enable_7_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_6_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_5_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_4_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_3_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_2_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_1_s;
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wire [(CH_SCNT-1):0] dac_dmx_enable_0_s;
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// loop variables
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genvar n;
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assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 |
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dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0;
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assign upack_valid_0 = | dac_dmx_enable & dac_enable_0 & dac_xfer_out;
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assign upack_valid_1 = | dac_dmx_enable & dac_enable_1 & dac_xfer_out;
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assign upack_valid_2 = | dac_dmx_enable & dac_enable_2 & dac_xfer_out;
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assign upack_valid_3 = | dac_dmx_enable & dac_enable_3 & dac_xfer_out;
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assign upack_valid_4 = | dac_dmx_enable & dac_enable_4 & dac_xfer_out;
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assign upack_valid_5 = | dac_dmx_enable & dac_enable_5 & dac_xfer_out;
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assign upack_valid_6 = | dac_dmx_enable & dac_enable_6 & dac_xfer_out;
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assign upack_valid_7 = | dac_dmx_enable & dac_enable_7 & dac_xfer_out;
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always @(posedge dac_clk) begin
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xfer_valid_d1 <= dma_xfer_in;
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xfer_valid_d2 <= xfer_valid_d1;
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xfer_valid_d3 <= xfer_valid_d2;
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xfer_valid_d4 <= xfer_valid_d3;
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xfer_valid_d5 <= xfer_valid_d4;
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if (dac_dmx_enable[NUM_OF_CHANNELS_P-1] == 1'b1) begin
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dac_xfer_out <= xfer_valid_d4;
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end else begin
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dac_xfer_out <= xfer_valid_d5;
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end
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end
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always @(posedge dac_clk) begin
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dac_valid <= dac_dsf_valid_s[7] | dac_dsf_valid_s[6] |
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dac_dsf_valid_s[5] | dac_dsf_valid_s[4] |
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dac_dsf_valid_s[3] | dac_dsf_valid_s[2] |
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dac_dsf_valid_s[1] | dac_dsf_valid_s[0];
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dac_sync <= dac_dsf_sync_s[7] | dac_dsf_sync_s[6] |
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dac_dsf_sync_s[5] | dac_dsf_sync_s[4] |
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dac_dsf_sync_s[3] | dac_dsf_sync_s[2] |
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dac_dsf_sync_s[1] | dac_dsf_sync_s[0];
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dac_dsf_data <= dac_dsf_data_s[7] | dac_dsf_data_s[6] |
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dac_dsf_data_s[5] | dac_dsf_data_s[4] |
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dac_dsf_data_s[3] | dac_dsf_data_s[2] |
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dac_dsf_data_s[1] | dac_dsf_data_s[0];
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dac_dmx_enable[7] <= | dac_dmx_enable_7_s;
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dac_dmx_enable[6] <= | dac_dmx_enable_6_s;
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dac_dmx_enable[5] <= | dac_dmx_enable_5_s;
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dac_dmx_enable[4] <= | dac_dmx_enable_4_s;
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dac_dmx_enable[3] <= | dac_dmx_enable_3_s;
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dac_dmx_enable[2] <= | dac_dmx_enable_2_s;
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dac_dmx_enable[1] <= | dac_dmx_enable_1_s;
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dac_dmx_enable[0] <= | dac_dmx_enable_0_s;
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end
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// store & fwd
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generate
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if (NUM_OF_CHANNELS_P < NUM_OF_CHANNELS_M) begin
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for (n = NUM_OF_CHANNELS_P; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_def
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assign dac_dsf_valid_s[n] = 'd0;
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assign dac_dsf_sync_s[n] = 'd0;
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assign dac_dsf_data_s[n] = 'd0;
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end
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end
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for (n = 0; n < NUM_OF_CHANNELS_P; n = n + 1) begin: g_dsf
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util_upack_dsf #(
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.NUM_OF_CHANNELS_P (NUM_OF_CHANNELS_P),
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.NUM_OF_CHANNELS_M (NUM_OF_CHANNELS_M),
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.CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH),
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.NUM_OF_CHANNELS_O ((n+1)))
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i_dsf (
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.dac_clk (dac_clk),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data),
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.dac_dmx_enable (dac_dmx_enable[n]),
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.dac_dsf_valid (dac_dsf_valid_s[n]),
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.dac_dsf_sync (dac_dsf_sync_s[n]),
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.dac_dsf_data (dac_dsf_data_s[n]));
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end
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endgenerate
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// demux
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generate
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for (n = 0; n < CH_SCNT; n = n + 1) begin: g_dmx
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util_upack_dmx i_dmx (
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.dac_clk (dac_clk),
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.dac_enable ({dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4,
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dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0}),
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.dac_data_0 (dac_data_0[((16*n)+15):(16*n)]),
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.dac_data_1 (dac_data_1[((16*n)+15):(16*n)]),
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.dac_data_2 (dac_data_2[((16*n)+15):(16*n)]),
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.dac_data_3 (dac_data_3[((16*n)+15):(16*n)]),
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.dac_data_4 (dac_data_4[((16*n)+15):(16*n)]),
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.dac_data_5 (dac_data_5[((16*n)+15):(16*n)]),
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.dac_data_6 (dac_data_6[((16*n)+15):(16*n)]),
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.dac_data_7 (dac_data_7[((16*n)+15):(16*n)]),
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.dac_dmx_enable ({dac_dmx_enable_7_s[n], dac_dmx_enable_6_s[n],
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dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n],
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dac_dmx_enable_3_s[n], dac_dmx_enable_2_s[n],
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dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}),
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.dac_dsf_data (dac_dsf_data[((NUM_OF_CHANNELS_M*16*(n+1))-1):(NUM_OF_CHANNELS_M*16*n)]));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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