291 lines
11 KiB
Verilog
291 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module axi_ad9361_rx_pnmon #(
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parameter Q_OR_I_N = 0,
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parameter PRBS_SEL = 0) (
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// adc interface
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input adc_clk,
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input adc_valid,
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input [11:0] adc_data_i,
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input [11:0] adc_data_q,
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// pn out of sync and error
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input [ 3:0] adc_pnseq_sel,
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output adc_pn_oos,
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output adc_pn_err);
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localparam PRBS_P09 = 0;
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localparam PRBS_P11 = 1;
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localparam PRBS_P15 = 2;
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localparam PRBS_P20 = 3;
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// internal registers
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reg adc_pn0_valid = 'd0;
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reg [15:0] adc_pn0_data = 'd0;
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reg adc_pn0_valid_in = 'd0;
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reg [15:0] adc_pn0_data_in = 'd0;
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reg [15:0] adc_pn0_data_pn = 'd0;
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reg adc_pn1_valid_t = 'd0;
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reg [11:0] adc_pn1_data_d = 'd0;
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reg adc_pn1_valid_in = 'd0;
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reg [23:0] adc_pn1_data_in = 'd0;
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reg [23:0] adc_pn1_data_pn = 'd0;
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reg adc_pn_valid_in = 'd0;
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reg [23:0] adc_pn_data_in = 'd0;
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reg [23:0] adc_pn_data_pn = 'd0;
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// internal signals
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wire [11:0] adc_pn0_data_i_s;
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wire [11:0] adc_pn0_data_q_s;
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wire [11:0] adc_pn0_data_q_rev_s;
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wire [15:0] adc_pn0_data_s;
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wire adc_pn0_iq_match_s;
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wire [15:0] adc_pn0_data_pn_s;
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wire adc_pn1_valid_s;
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wire [23:0] adc_pn1_data_pn_s;
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// bit reversal function
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function [11:0] brfn;
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input [11:0] din;
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reg [11:0] dout;
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begin
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dout[11] = din[ 0];
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dout[10] = din[ 1];
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dout[ 9] = din[ 2];
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dout[ 8] = din[ 3];
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dout[ 7] = din[ 4];
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dout[ 6] = din[ 5];
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dout[ 5] = din[ 6];
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dout[ 4] = din[ 7];
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dout[ 3] = din[ 8];
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dout[ 2] = din[ 9];
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dout[ 1] = din[10];
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dout[ 0] = din[11];
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brfn = dout;
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end
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endfunction
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// device-specific prbs function
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function [15:0] pn0fn;
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input [15:0] din;
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reg [15:0] dout;
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begin
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dout = {din[14:0], ((^din[15:4]) ^ (^din[2:1]))};
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pn0fn = dout;
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end
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endfunction
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// standard prbs functions
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function [23:0] pn1fn;
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input [23:0] din;
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reg [23:0] dout;
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begin
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case (PRBS_SEL)
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PRBS_P09: begin
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dout[23] = din[ 8] ^ din[ 4];
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dout[22] = din[ 7] ^ din[ 3];
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dout[21] = din[ 6] ^ din[ 2];
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dout[20] = din[ 5] ^ din[ 1];
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dout[19] = din[ 4] ^ din[ 0];
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dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
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dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
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dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
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dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
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dout[14] = din[ 8] ^ din[ 0];
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dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
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dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
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dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
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dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
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dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
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dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
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dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
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dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
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dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
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dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
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dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
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end
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PRBS_P11: begin
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dout[23] = din[10] ^ din[ 8];
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dout[22] = din[ 9] ^ din[ 7];
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dout[21] = din[ 8] ^ din[ 6];
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dout[20] = din[ 7] ^ din[ 5];
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dout[19] = din[ 6] ^ din[ 4];
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dout[18] = din[ 5] ^ din[ 3];
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dout[17] = din[ 4] ^ din[ 2];
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dout[16] = din[ 3] ^ din[ 1];
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dout[15] = din[ 2] ^ din[ 0];
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dout[14] = din[ 1] ^ din[10] ^ din[ 8];
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dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
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dout[12] = din[10] ^ din[ 6];
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dout[11] = din[ 9] ^ din[ 5];
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dout[10] = din[ 8] ^ din[ 4];
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dout[ 9] = din[ 7] ^ din[ 3];
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dout[ 8] = din[ 6] ^ din[ 2];
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dout[ 7] = din[ 5] ^ din[ 1];
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dout[ 6] = din[ 4] ^ din[ 0];
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dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
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dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
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dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
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dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
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dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
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dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
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end
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PRBS_P15: begin
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dout[23] = din[14] ^ din[13];
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dout[22] = din[13] ^ din[12];
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dout[21] = din[12] ^ din[11];
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dout[20] = din[11] ^ din[10];
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dout[19] = din[10] ^ din[ 9];
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dout[18] = din[ 9] ^ din[ 8];
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dout[17] = din[ 8] ^ din[ 7];
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dout[16] = din[ 7] ^ din[ 6];
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dout[15] = din[ 6] ^ din[ 5];
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dout[14] = din[ 5] ^ din[ 4];
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dout[13] = din[ 4] ^ din[ 3];
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dout[12] = din[ 3] ^ din[ 2];
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dout[11] = din[ 2] ^ din[ 1];
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dout[10] = din[ 1] ^ din[ 0];
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dout[ 9] = din[ 0] ^ din[14] ^ din[13];
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dout[ 8] = din[14] ^ din[12];
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dout[ 7] = din[13] ^ din[11];
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dout[ 6] = din[12] ^ din[10];
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dout[ 5] = din[11] ^ din[ 9];
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dout[ 4] = din[10] ^ din[ 8];
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dout[ 3] = din[ 9] ^ din[ 7];
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dout[ 2] = din[ 8] ^ din[ 6];
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dout[ 1] = din[ 7] ^ din[ 5];
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dout[ 0] = din[ 6] ^ din[ 4];
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end
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PRBS_P20: begin
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dout[23] = din[19] ^ din[ 2];
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dout[22] = din[18] ^ din[ 1];
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dout[21] = din[17] ^ din[ 0];
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dout[20] = din[16] ^ din[19] ^ din[ 2];
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dout[19] = din[15] ^ din[18] ^ din[ 1];
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dout[18] = din[14] ^ din[17] ^ din[ 0];
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dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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end
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endcase
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pn1fn = dout;
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end
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endfunction
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// device specific, assuming lower nibble is lost-
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assign adc_pn0_data_i_s = (Q_OR_I_N == 1) ? adc_data_q : adc_data_i;
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assign adc_pn0_data_q_s = (Q_OR_I_N == 1) ? adc_data_i : adc_data_q;
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assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s);
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assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]};
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assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
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assign adc_pn0_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn0_data_in : adc_pn0_data_pn;
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always @(posedge adc_clk) begin
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adc_pn0_valid <= adc_valid;
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adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s;
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adc_pn0_valid_in <= adc_pn0_valid;
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if (adc_pn0_valid == 1'b1) begin
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adc_pn0_data_in <= adc_pn0_data;
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adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s);
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end
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end
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// standard, runs on 24bit
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assign adc_pn1_valid_s = adc_pn1_valid_t & adc_valid;
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assign adc_pn1_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn1_data_in : adc_pn1_data_pn;
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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adc_pn1_valid_t <= ~adc_pn1_valid_t;
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adc_pn1_data_d <= adc_data_i;
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end
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adc_pn1_valid_in <= adc_pn1_valid_s;
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if (adc_pn1_valid_s == 1'b1) begin
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adc_pn1_data_in <= {adc_pn1_data_d, adc_data_i};
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adc_pn1_data_pn <= pn1fn(adc_pn1_data_pn_s);
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end
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end
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// pn mux
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always @(posedge adc_clk) begin
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if (adc_pnseq_sel == 4'h9) begin
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adc_pn_valid_in <= adc_pn1_valid_in;
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adc_pn_data_in <= adc_pn1_data_in;
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adc_pn_data_pn <= adc_pn1_data_pn;
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end else begin
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adc_pn_valid_in <= adc_pn0_valid_in;
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adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in};
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adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn};
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end
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end
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// pn oos & pn err
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ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
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.adc_clk (adc_clk),
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.adc_valid_in (adc_pn_valid_in),
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.adc_data_in (adc_pn_data_in),
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.adc_data_pn (adc_pn_data_pn),
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.adc_pn_oos (adc_pn_oos),
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.adc_pn_err (adc_pn_err));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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