245 lines
6.3 KiB
Verilog
245 lines
6.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9963_if #(
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// this parameter controls the buffer type based on the target device.
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parameter DEVICE_TYPE = 0,
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parameter ADC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive)
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input trx_clk,
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input trx_iq,
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input [11:0] trx_data,
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// physical interface (transmit)
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input tx_clk,
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output tx_iq,
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output [11:0] tx_data,
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// clock (common to both receive and transmit)
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input adc_rst,
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input dac_rst,
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output adc_clk,
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output dac_clk,
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// receive data path interface
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output reg adc_valid,
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output reg [23:0] adc_data,
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output reg adc_status,
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input up_adc_ce,
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// transmit data path interface
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input dac_valid,
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input [23:0] dac_data,
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input up_dac_ce,
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// delay interface
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input up_clk,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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reg [11:0] rx_data_p = 0;
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reg [11:0] tx_data_p = 'd0;
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reg [11:0] tx_data_n = 'd0;
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// internal signals
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wire [11:0] rx_data_p_s;
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wire [11:0] rx_data_n_s;
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wire rx_iq_p_s;
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wire rx_iq_n_s;
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wire div_clk;
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genvar l_inst;
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always @(posedge adc_clk) begin
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if( rx_iq_p_s == 1'b1) begin
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adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I
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adc_valid <= 1'b1; // data[23:12] Q
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end else begin
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rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge
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adc_data <= {rx_data_p, rx_data_n_s}; // so we take current N data with previous P data
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adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA
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end
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end
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always @(posedge dac_clk) begin
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if(dac_valid == 1'b1) begin
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tx_data_p <= dac_data[11:0] ;
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tx_data_n <= dac_data[23:12];
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end
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end
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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// device clock interface (receive clock)
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BUFGCTRL #(
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.INIT_OUT(0),
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.PRESELECT_I0("FALSE"),
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.PRESELECT_I1("FALSE")
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)
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bufgctrl_adc (
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.O(adc_clk),
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.CE0(1'b1),
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.CE1(1'b0),
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.I0(trx_clk),
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.I1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.S0(up_adc_ce),
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.S1(1'b0)
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);
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// receive data interface, ibuf -> idelay -> iddr
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_data (
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.rx_clk (adc_clk),
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.rx_data_in_p (trx_data[l_inst]),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_data_p_s[l_inst]),
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.rx_data_n (rx_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[l_inst]),
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.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// receive iq interface, ibuf -> idelay -> iddr
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_iq (
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.rx_clk (adc_clk),
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.rx_data_in_p (trx_iq),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_iq_p_s),
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.rx_data_n (rx_iq_n_s),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[12]),
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.up_dwdata (up_adc_dwdata[64:60]),
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.up_drdata (up_adc_drdata[64:60]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// transmit data interface
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BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (tx_clk),
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.O (div_clk));
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BUFGCTRL #(
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.INIT_OUT(0),
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.PRESELECT_I0("FALSE"),
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.PRESELECT_I1("FALSE")
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)
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bufgctrl_dac (
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.O(dac_clk),
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.CE0(1'b1),
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.CE1(1'b0),
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.I0(div_clk),
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.I1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.S0(up_dac_ce),
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.S1(1'b0)
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);
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("SYNC"))
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i_tx_data_oddr (
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.CE (1'b1),
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.R (dac_rst),
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.S (1'b0),
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.C (dac_clk),
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.D1 (tx_data_p[l_inst]),
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.D2 (tx_data_n[l_inst]),
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.Q (tx_data[l_inst]));
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end
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endgenerate
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("SYNC"))
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i_tx_data_oddr (
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.CE (1'b1),
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.R (dac_rst),
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.S (1'b0),
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.C (dac_clk),
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.D1 (1'b1),
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.D2 (1'b0),
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.Q (tx_iq));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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