128 lines
3.9 KiB
Verilog
128 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module dmac_2d_transfer (
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input req_aclk,
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input req_aresetn,
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input req_valid,
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output reg req_ready,
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input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
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input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
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input [DMA_LENGTH_WIDTH-1:0] req_x_length,
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input [DMA_LENGTH_WIDTH-1:0] req_y_length,
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input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
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input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
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input req_sync_transfer_start,
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output reg req_eot,
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output reg out_req_valid,
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input out_req_ready,
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output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
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output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
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output [DMA_LENGTH_WIDTH-1:0] out_req_length,
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output reg out_req_sync_transfer_start,
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input out_eot
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);
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parameter DMA_LENGTH_WIDTH = 24;
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parameter BYTES_PER_BEAT_WIDTH_SRC = 3;
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parameter BYTES_PER_BEAT_WIDTH_DEST = 3;
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reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address;
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reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address;
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reg [DMA_LENGTH_WIDTH-1:0] x_length;
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reg [DMA_LENGTH_WIDTH-1:0] y_length;
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reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
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reg [DMA_LENGTH_WIDTH-1:0] src_stride;
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reg [1:0] req_id;
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reg [1:0] eot_id;
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reg [3:0] last_req;
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assign out_req_dest_address = dest_address;
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assign out_req_src_address = src_address;
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assign out_req_length = x_length;
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always @(posedge req_aclk)
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begin
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if (req_aresetn == 1'b0) begin
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req_id <= 2'b0;
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eot_id <= 2'b0;
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req_eot <= 1'b0;
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end else begin
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if (out_req_valid && out_req_ready) begin
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req_id <= req_id + 1'b1;
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last_req[req_id] <= y_length == 0;
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end
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req_eot <= 1'b0;
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if (out_eot) begin
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eot_id <= eot_id + 1'b1;
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req_eot <= last_req[eot_id];
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end
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end
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end
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always @(posedge req_aclk)
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begin
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if (req_aresetn == 1'b0) begin
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dest_address <= 'h00;
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src_address <= 'h00;
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x_length <= 'h00;
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y_length <= 'h00;
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dest_stride <= 'h00;
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src_stride <= 'h00;
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req_ready <= 1'b1;
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out_req_valid <= 1'b0;
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out_req_sync_transfer_start <= 1'b0;
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end else begin
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if (req_ready) begin
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if (req_valid) begin
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dest_address <= req_dest_address;
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src_address <= req_src_address;
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x_length <= req_x_length;
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y_length <= req_y_length;
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dest_stride <= req_dest_stride;
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src_stride <= req_src_stride;
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out_req_sync_transfer_start <= req_sync_transfer_start;
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req_ready <= 1'b0;
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out_req_valid <= 1'b1;
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end
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end else begin
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if (out_req_valid && out_req_ready) begin
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dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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y_length <= y_length - 1'b1;
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out_req_sync_transfer_start <= 1'b0;
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if (y_length == 0) begin
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out_req_valid <= 1'b0;
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req_ready <= 1'b1;
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end
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end
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end
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end
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end
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endmodule
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