109 lines
2.9 KiB
Verilog
109 lines
2.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module dmac_src_axi_stream (
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input s_axis_aclk,
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input s_axis_aresetn,
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input enable,
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output enabled,
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input sync_id,
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output sync_id_ret,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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input eot,
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output s_axis_ready,
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input s_axis_valid,
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input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
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input [0:0] s_axis_user,
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output s_axis_xfer_req,
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input fifo_ready,
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output fifo_valid,
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output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
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input req_valid,
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output req_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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input req_sync_transfer_start
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);
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parameter ID_WIDTH = 3;
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parameter S_AXIS_DATA_WIDTH = 64;
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parameter LENGTH_WIDTH = 24;
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parameter BEATS_PER_BURST_WIDTH = 4;
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reg needs_sync = 1'b0;
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wire sync = s_axis_user[0];
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wire has_sync = ~needs_sync | sync;
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wire sync_valid = s_axis_valid & has_sync;
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assign sync_id_ret = sync_id;
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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needs_sync <= 1'b0;
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end else begin
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if (s_axis_valid && s_axis_ready && sync) begin
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needs_sync <= 1'b0;
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end else if (req_valid && req_ready) begin
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needs_sync <= req_sync_transfer_start;
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end
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end
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end
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dmac_data_mover # (
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.ID_WIDTH(ID_WIDTH),
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.DATA_WIDTH(S_AXIS_DATA_WIDTH),
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.DISABLE_WAIT_FOR_ID(0),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
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) i_data_mover (
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.clk(s_axis_aclk),
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.resetn(s_axis_aresetn),
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.enable(enable),
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.enabled(enabled),
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.sync_id(sync_id),
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.xfer_req(s_axis_xfer_req),
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.request_id(request_id),
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.response_id(response_id),
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.eot(eot),
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.req_valid(req_valid),
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.req_ready(req_ready),
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.req_last_burst_length(req_last_burst_length),
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.s_axi_ready(s_axis_ready),
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.s_axi_valid(sync_valid),
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.s_axi_data(s_axis_data),
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.m_axi_ready(fifo_ready),
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.m_axi_valid(fifo_valid),
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.m_axi_data(fifo_data)
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);
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endmodule
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