119 lines
3.5 KiB
VHDL
119 lines
3.5 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity i2s_clkgen is
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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enable : in Boolean ; -- Enable clockgen
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tick : in std_logic;
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bclk_div_rate : in natural range 0 to 255;
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lrclk_div_rate : in natural range 0 to 255;
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bclk : out std_logic; -- Bit Clock
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lrclk : out std_logic; -- Frame Clock
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channel_sync : out std_logic;
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frame_sync : out std_logic
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);
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end i2s_clkgen;
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architecture Behavioral of i2s_clkgen is
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signal reset_int : Boolean;
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signal prev_bclk_div_rate : natural range 0 to 255;
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signal prev_lrclk_div_rate : natural range 0 to 255;
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signal bclk_count : natural range 0 to 255;
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signal lrclk_count : natural range 0 to 255;
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signal bclk_int : std_logic;
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signal lrclk_int : std_logic;
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signal lrclk_tick : Boolean;
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begin
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reset_int <= resetn = '0' or not enable;
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bclk <= bclk_int;
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lrclk <= lrclk_int;
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-----------------------------------------------------------------------------------
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-- Serial clock generation BCLK_O
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-----------------------------------------------------------------------------------
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bclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_bclk_div_rate <= bclk_div_rate;
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if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
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bclk_int <= '1';
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bclk_count <= bclk_div_rate;
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else
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if tick = '1' then
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if bclk_count = bclk_div_rate then
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bclk_count <= 0;
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bclk_int <= not bclk_int;
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else
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bclk_count <= bclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process bclk_gen;
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lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
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channel_sync <= '1' when lrclk_count = 1 else '0';
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frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
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-----------------------------------------------------------------------------------
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-- Frame clock generator LRCLK_O
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-----------------------------------------------------------------------------------
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lrclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_lrclk_div_rate <= lrclk_div_rate;
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-- Reset
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if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
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lrclk_int <= '1';
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lrclk_count <= lrclk_div_rate;
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else
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if lrclk_tick then
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if lrclk_count = lrclk_div_rate then
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lrclk_count <= 0;
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lrclk_int <= not lrclk_int;
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else
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lrclk_count <= lrclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process lrclk_gen;
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end Behavioral;
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