120 lines
3.4 KiB
VHDL
120 lines
3.4 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity i2s_tx is
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generic(
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C_SLOT_WIDTH : integer := 24; -- Width of one Slot
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C_NUM : integer := 1
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);
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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enable : in Boolean; -- Enable TX
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bclk : in std_logic; -- Bit Clock
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channel_sync : in std_logic; -- Channel Sync
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frame_sync : in std_logic; -- Frame Sync
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sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output
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ack : out std_logic; -- Request new Slot Data
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stb : in std_logic; -- Request new Slot Data
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data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in
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);
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end i2s_tx;
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architecture Behavioral of i2s_tx is
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type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0);
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signal data_int : mem;
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signal reset_int : Boolean;
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signal enable_int : Boolean;
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signal bit_sync : std_logic;
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signal channel_sync_int : std_logic;
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signal frame_sync_int : std_logic;
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signal channel_sync_int_d1 : std_logic;
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signal bclk_d1 : std_logic;
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begin
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reset_int <= resetn = '0' or not enable;
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process (clk)
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begin
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if rising_edge(clk) then
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if resetn = '0' then
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bclk_d1 <= '0';
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channel_sync_int_d1 <= '0';
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else
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bclk_d1 <= bclk;
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channel_sync_int_d1 <= channel_sync_int;
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end if;
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end if;
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end process;
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bit_sync <= (bclk xor bclk_d1) and not bclk;
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channel_sync_int <= channel_sync and bit_sync;
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frame_sync_int <= frame_sync and bit_sync;
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ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0';
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gen: for i in 0 to C_NUM - 1 generate
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serialize_data: process(clk)
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begin
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if rising_edge(clk) then
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if reset_int then
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data_int(i)(31 downto 0) <= (others => '0');
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elsif bit_sync = '1' then
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if channel_sync_int = '1' then
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data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data;
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data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0');
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else
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data_int(i) <= data_int(i)(30 downto 0) & '0';
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end if;
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end if;
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end if;
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end process serialize_data;
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sdata(i) <= data_int(i)(31) when enable_int else '0';
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end generate;
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enable_sync: process (clk)
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begin
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if rising_edge(clk) then
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if reset_int then
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enable_int <= False;
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else
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if enable and frame_sync_int = '1' and stb = '1' then
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enable_int <= True;
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elsif not enable then
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enable_int <= False;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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