Istvan Csomortani dee108ba22 fmcomms8/intel: Fix fPLL configuration ... When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel.		2021-01-12 19:34:44 +02:00
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fmcomms8_bd.tcl	fmcomms8: Changed the interrupt addresses to be similar with adrv9009zu11eg project	2020-03-06 16:07:02 +02:00
fmcomms8_qsys.tcl	fmcomms8/intel: Fix fPLL configuration	2021-01-12 19:34:44 +02:00
fmcomms8_spi.v	fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive	2020-09-25 11:54:12 +03:00