58 lines
716 B
Verilog
Executable File
58 lines
716 B
Verilog
Executable File
// HIERARCHY
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// ENDHIERARCHY
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`ifndef xlConvPkgIncluded
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`define xlConvPkgIncluded 1
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`endif
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// synopsys translate_off
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`ifndef simulating
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`define simulating 1
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`endif
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// synopsys translate_on
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`ifndef simulating
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`define simulating 0
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`endif
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`ifndef xlUnsigned
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`define xlUnsigned 1
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`endif
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`ifndef xlSigned
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`define xlSigned 2
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`endif
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`ifndef xlFloat
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`define xlFloat 3
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`endif
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`ifndef xlWrap
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`define xlWrap 1
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`endif
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`ifndef xlSaturate
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`define xlSaturate 2
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`endif
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`ifndef xlTruncate
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`define xlTruncate 1
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`endif
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`ifndef xlRound
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`define xlRound 2
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`endif
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`ifndef xlRoundBanker
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`define xlRoundBanker 3
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`endif
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`ifndef xlAddMode
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`define xlAddMode 1
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`endif
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`ifndef xlSubMode
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`define xlSubMode 2
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`endif
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