125 lines
3.4 KiB
Verilog
125 lines
3.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module src_fifo_inf #(
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parameter ID_WIDTH = 3,
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parameter DATA_WIDTH = 64,
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parameter BEATS_PER_BURST_WIDTH = 4
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) (
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input clk,
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input resetn,
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input enable,
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output enabled,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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input eot,
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output bl_valid,
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input bl_ready,
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output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
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input en,
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input [DATA_WIDTH-1:0] din,
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output reg overflow,
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input sync,
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output xfer_req,
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output fifo_valid,
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output [DATA_WIDTH-1:0] fifo_data,
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output fifo_last,
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input req_valid,
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output req_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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input req_sync_transfer_start
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);
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wire ready;
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wire valid;
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assign enabled = enable;
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assign valid = en & ready;
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always @(posedge clk)
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begin
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if (enable) begin
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overflow <= en & ~ready;
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end else begin
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overflow <= en;
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end
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end
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data_mover #(
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.ID_WIDTH(ID_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
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) i_data_mover (
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.clk(clk),
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.resetn(resetn),
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.xfer_req(xfer_req),
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.request_id(request_id),
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.response_id(response_id),
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.eot(eot),
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.bl_valid(bl_valid),
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.bl_ready(bl_ready),
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.measured_last_burst_length(measured_last_burst_length),
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.req_valid(req_valid),
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.req_ready(req_ready),
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.req_last_burst_length(req_last_burst_length),
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.req_sync_transfer_start(req_sync_transfer_start),
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.req_xlast(1'b0),
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.s_axi_ready(ready),
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.s_axi_valid(valid),
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.s_axi_data(din),
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.s_axi_sync(sync),
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.s_axi_last(1'b0),
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.m_axi_valid(fifo_valid),
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.m_axi_data(fifo_data),
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.m_axi_last(fifo_last));
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endmodule
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