99 lines
3.7 KiB
Verilog
99 lines
3.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved. Confidential and proprietary.
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//
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// Do not redistribute without explicit permission.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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module jesd204_ilas_config_static #(
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parameter DID = 8'h00,
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parameter BID = 4'h0,
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parameter L = 5'h3,
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parameter SCR = 1'b1,
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parameter F = 8'h01,
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parameter K = 5'h1f,
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parameter M = 8'h3,
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parameter N = 5'h0f,
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parameter CS = 2'h0,
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parameter NP = 5'h0f,
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parameter SUBCLASSV = 3'h1,
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parameter S = 5'h00,
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parameter JESDV = 3'h1,
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parameter CF = 5'h00,
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parameter HD = 1'b1,
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parameter NUM_LANES = 1
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) (
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input clk,
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input [1:0] ilas_config_addr,
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input ilas_config_rd,
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output reg [32*NUM_LANES-1:0] ilas_config_data
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);
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wire [31:0] ilas_mem[0:3];
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assign ilas_mem[0][15:0] = 8'h00;
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assign ilas_mem[0][23:16] = DID; // DID
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assign ilas_mem[0][27:24] = BID; // BID
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assign ilas_mem[0][31:28] = 4'h0; // ADJCNT
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assign ilas_mem[1][4:0] = 5'h00; // LID
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assign ilas_mem[1][5] = 1'b0; // PHADJ
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assign ilas_mem[1][6] = 1'b0; // ADJDIR
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assign ilas_mem[1][7] = 1'b0; // X
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assign ilas_mem[1][12:8] = L; // L
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assign ilas_mem[1][14:13] = 2'b00; // X
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assign ilas_mem[1][15] = SCR; // SCR
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assign ilas_mem[1][23:16] = F; // F
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assign ilas_mem[1][28:24] = K; // K
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assign ilas_mem[1][31:29] = 3'b000; // X
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assign ilas_mem[2][7:0] = M; // M
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assign ilas_mem[2][12:8] = N; // N
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assign ilas_mem[2][13] = 1'b0; // X
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assign ilas_mem[2][15:14] = CS; // CS
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assign ilas_mem[2][20:16] = NP; // N'
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assign ilas_mem[2][23:21] = SUBCLASSV; // SUBCLASSV
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assign ilas_mem[2][28:24] = S; // S
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assign ilas_mem[2][31:29] = JESDV; // JESDV
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assign ilas_mem[3][4:0] = CF; // CF
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assign ilas_mem[3][6:5] = 2'b00; // X
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assign ilas_mem[3][7] = HD; // HD
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assign ilas_mem[3][23:8] = 16'h0000; // X
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assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
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ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] +
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ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] +
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ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] +
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ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] +
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ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7];
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generate
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genvar i;
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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always @(posedge clk) begin
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if (ilas_config_rd == 1'b1) begin
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ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr];
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/* Overwrite special cases */
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case (ilas_config_addr)
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'h1: ilas_config_data[i*32+4:i*32] <= i;
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'h3: ilas_config_data[i*32+31:i*32+24] <= ilas_mem[ilas_config_addr][31:24] + i;
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endcase
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end
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end
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end
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endgenerate
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endmodule
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