249 lines
7.9 KiB
Verilog
249 lines
7.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_axis_dma_rx (
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// adc interface
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adc_clk,
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adc_rst,
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// dma interface
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dma_clk,
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dma_rst,
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dma_start,
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dma_stream,
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dma_count,
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dma_ovf,
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dma_unf,
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dma_status,
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dma_bw,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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localparam PCORE_VERSION = 32'h00050063;
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parameter PCORE_ID = 0;
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// adc interface
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input adc_clk;
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output adc_rst;
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// dma interface
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input dma_clk;
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output dma_rst;
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output dma_start;
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output dma_stream;
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output [31:0] dma_count;
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input dma_ovf;
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input dma_unf;
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input dma_status;
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input [31:0] dma_bw;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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reg up_dma_stream = 'd0;
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reg up_dma_start = 'd0;
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reg [31:0] up_dma_count = 'd0;
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reg up_dma_ovf = 'd0;
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reg up_dma_unf = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg dma_start_d = 'd0;
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reg dma_start_2d = 'd0;
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reg dma_start = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_preset_s;
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wire up_dma_ovf_s;
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wire up_dma_unf_s;
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wire up_dma_status_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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assign up_preset_s = ~up_resetn;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_resetn <= 'd0;
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up_dma_stream <= 'd0;
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up_dma_start <= 'd0;
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up_dma_count <= 'd0;
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up_dma_ovf <= 'd0;
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up_dma_unf <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_resetn <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
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up_dma_stream <= up_wdata[1];
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up_dma_start <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
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up_dma_count <= up_wdata;
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end
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if (up_dma_ovf_s == 1'b1) begin
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up_dma_ovf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
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up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
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end
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if (up_dma_unf_s == 1'b1) begin
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up_dma_unf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
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up_dma_unf <= up_dma_unf & ~up_wdata[1];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= PCORE_ID;
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8'h02: up_rdata <= up_scratch;
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8'h10: up_rdata <= {31'd0, up_resetn};
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8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
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8'h21: up_rdata <= up_dma_count;
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8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s};
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8'h23: up_rdata <= dma_bw;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
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ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst));
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// dma control & status
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up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_dma_start,
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up_dma_stream,
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up_dma_count}),
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.d_rst (dma_rst),
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.d_clk (dma_clk),
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.d_data_cntrl ({ dma_start_s,
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dma_stream,
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dma_count}));
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up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status ({up_dma_ovf_s,
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up_dma_unf_s,
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up_dma_status_s}),
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.d_rst (dma_rst),
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.d_clk (dma_clk),
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.d_data_status ({ dma_ovf,
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dma_unf,
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dma_status}));
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// start needs to be a pulse
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always @(posedge dma_clk) begin
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dma_start_d <= dma_start_s;
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dma_start_2d <= dma_start_d;
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dma_start <= dma_start_d & ~dma_start_2d;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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